公开(公告)号：US20150249130A1

公开(公告)日：2015-09-03

申请号：US14713349

申请日：2015-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong-Jong JEONG ,  Jeong-Yun Lee ,  Shi Li Quan ,  Dong-Suk Shin ,  Si-Hyung Lee

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/41758 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7851

Abstract: Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin. The method may also include forming a first recess in the fin having a first width and a first depth and forming a second recess in the first recess having a second width that is less than the first width and having a second depth that is greater than the first depth. The method may further include forming a source/drain region in the first and second recesses.

公开(公告)号：US09034700B1

公开(公告)日：2015-05-19

申请号：US14491044

申请日：2014-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong-Jong Jeong ,  Jeong-Yun Lee ,  Shi Ii Quan ,  Dong-Suk Shin ,  Si-Hyung Lee

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/0847 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/41758 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7851

Abstract: Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin. The method may also include forming a first recess in the fin having a first width and a first depth and forming a second recess in the first recess having a second width that is less than the first width and having a second depth that is greater than the first depth. The method may further include forming a source/drain region in the first and second recesses.

Abstract translation: 提供包括Fin场效应晶体管（finFET）的集成电路器件以及形成这些器件的方法。 所述方法可以包括在衬底上形成翅片并在翅片上形成栅极线。 该方法还可以包括在翅片中形成具有第一宽度和第一深度的第一凹部，并且在第一凹部中形成具有小于第一宽度的第二宽度的第二凹部，并且具有大于 第一深度 该方法还可以包括在第一和第二凹部中形成源极/漏极区域。

公开(公告)号：US20150140759A1

公开(公告)日：2015-05-21

申请号：US14491044

申请日：2014-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong-Jong JEONG ,  Jeong-Yun Lee ,  Shi li Quan ,  Dong-Suk Shin ,  Si-Hyung Lee

IPC: H01L29/66 ,  H01L29/10

CPC classification number: H01L29/0847 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/41758 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7851

Abstract: Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin. The method may also include forming a first recess in the fin having a first width and a first depth and forming a second recess in the first recess having a second width that is less than the first width and having a second depth that is greater than the first depth. The method may further include forming a source/drain region in the first and second recesses.

Abstract translation: 提供包括Fin场效应晶体管（finFET）的集成电路器件以及形成这些器件的方法。 所述方法可以包括在衬底上形成翅片并在翅片上形成栅极线。 该方法还可以包括在翅片中形成具有第一宽度和第一深度的第一凹部，并且在第一凹部中形成具有小于第一宽度的第二宽度的第二凹部，并且具有大于 第一深度 该方法还可以包括在第一和第二凹部中形成源极/漏极区域。

公开(公告)号：US09972717B2

公开(公告)日：2018-05-15

申请号：US15228421

申请日：2016-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong-Jong Jeong ,  Jeong-Yun Lee ,  Geo-Myung Shin ,  Dong-Suk Shin ,  Si-Hyung Lee ,  Seo-Jin Jeong

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/41 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device comprises a first multi-channel active pattern which is defined by a field insulating layer, extends along a first direction, and includes a first portion and a second portion; a gate electrode which extends along a second direction different from the first direction and is formed on the first portion; and a first source/drain region which is formed around the second portion protruding further upward than a top surface of the field insulating layer and contacts the field insulating layer, wherein the second portion is disposed on both sides of the first portion in the first direction and is more recessed than the first portion, a top surface of the first portion and a top surface of the second portion protrude further upward than the top surface of the field insulating layer, and a profile of sidewalls of the second portion is continuous.

公开(公告)号：US20160343859A1

公开(公告)日：2016-11-24

申请号：US15228421

申请日：2016-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong-Jong JEONG ,  Jeong-Yun Lee ,  Geo-Myung Shin ,  Dong-Suk Shin ,  Si-Hyung Lee ,  Seo-Jin Jeong

IPC: H01L29/78 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/06 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device comprises a first multi-channel active pattern which is defined by a field insulating layer, extends along a first direction, and includes a first portion and a second portion; a gate electrode which extends along a second direction different from the first direction and is formed on the first portion; and a first source/drain region which is formed around the second portion protruding further upward than a top surface of the field insulating layer and contacts the field insulating layer, wherein the second portion is disposed on both sides of the first portion in the first direction and is more recessed than the first portion, a top surface of the first portion and a top surface of the second portion protrude further upward than the top surface of the field insulating layer, and a profile of sidewalls of the second portion is continuous.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括由场绝缘层限定的第一多沟道有源图案，沿着第一方向延伸，并且包括第一部分和第二部分; 栅极电极，沿着与第一方向不同的第二方向延伸并形成在第一部分上; 以及第一源极/漏极区域，其围绕所述第二部分形成在所述场绝缘层的顶表面之上并且与所述场绝缘层接触的位置，其中所述第二部分设置在所述第一部分的所述第一方向的两侧 并且比第一部分更凹陷，第一部分的顶表面和第二部分的顶表面比场绝缘层的顶表面进一步向上突出，并且第二部分的侧壁的轮廓是连续的。

公开(公告)号：US20160141381A1

公开(公告)日：2016-05-19

申请号：US14816568

申请日：2015-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kook-Tae KIM ,  Ho-Sung Son ,  Geo-Myung Shin ,  Dong-Suk Shin ,  Si-Hyung Lee ,  Ji-Hye Yi ,  Sung-Hoon Jung ,  Yeong-Jong Jeong

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor devices and methods for fabricating the same are provided. The semiconductor devices include a fin active pattern formed to project from a substrate, a gate electrode formed to cross the fin active pattern on the substrate, a gate spacer formed on a side wall of the gate electrode and having a low dielectric constant and an elevated source/drain formed on both sides of the gate electrode on the fin active pattern. The gate spacer includes first, second and third spacers that sequentially come in contact with each other in a direction in which the gate spacer goes out from the gate electrode, and a carbon concentration of the second spacer is lower than carbon concentrations of the first and third spacers.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括从衬底突出形成的鳍状有源图案，形成为跨越衬底上的鳍状活性图案的栅极电极，形成在栅电极的侧壁上并具有低介电常数和升高的栅极间隔 源极/漏极形成在鳍状物图案上的栅电极的两侧。 栅极间隔物包括在栅极间隔物从栅电极出来的方向上依次相互接触的第一，第二和第三间隔物，第二间隔物的碳浓度低于第一和第二间隔物的碳浓度， 第三间隔物。

公开(公告)号：US09263521B2

公开(公告)日：2016-02-16

申请号：US14713349

申请日：2015-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong-Jong Jeong ,  Jeong-Yun Lee ,  Shi Li Quan ,  Dong-Suk Shin ,  Si-Hyung Lee

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L27/08 ,  H01L27/092 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/41758 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7851

Abstract: Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin. The method may also include forming a first recess in the fin having a first width and a first depth and forming a second recess in the first recess having a second width that is less than the first width and having a second depth that is greater than the first depth. The method may further include forming a source/drain region in the first and second recesses.