公开(公告)号：US09034700B1

公开(公告)日：2015-05-19

申请号：US14491044

申请日：2014-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong-Jong Jeong ,  Jeong-Yun Lee ,  Shi Ii Quan ,  Dong-Suk Shin ,  Si-Hyung Lee

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/0847 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/41758 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7851

Abstract: Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin. The method may also include forming a first recess in the fin having a first width and a first depth and forming a second recess in the first recess having a second width that is less than the first width and having a second depth that is greater than the first depth. The method may further include forming a source/drain region in the first and second recesses.

Abstract translation: 提供包括Fin场效应晶体管（finFET）的集成电路器件以及形成这些器件的方法。 所述方法可以包括在衬底上形成翅片并在翅片上形成栅极线。 该方法还可以包括在翅片中形成具有第一宽度和第一深度的第一凹部，并且在第一凹部中形成具有小于第一宽度的第二宽度的第二凹部，并且具有大于 第一深度 该方法还可以包括在第一和第二凹部中形成源极/漏极区域。

公开(公告)号：US20130270569A1

公开(公告)日：2013-10-17

申请号：US13915284

申请日：2013-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chongkwang Chang ,  Youngjoon Moon ,  Duck-nam Kim ,  Yeong-Jong Jeong

IPC: H01L29/04

CPC classification number: H01L29/04 ,  H01L21/28247 ,  H01L21/32137 ,  H01L21/32138 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4232 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern sequentially being stacked on the semiconductor substrate, a gate pattern including poly semiconductor and disposed on the metal-containing pattern, and a protective layer disposed on the gate pattern, wherein the protective layer includes oxide, nitride and/or oxynitride of the poly semiconductor.

Abstract translation: 半导体器件及其制造方法包括依次堆叠在半导体衬底上的半导体衬底，高k电介质图案和含金属图案，包括多晶半导体并设置在含金属图案上的栅极图案， 以及设置在所述栅极图案上的保护层，其中所述保护层包括所述多晶半导体的氧化物，氮化物和/或氧氮化物。

公开(公告)号：US20150132908A1

公开(公告)日：2015-05-14

申请号：US14294429

申请日：2014-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong-Jong Jeong ,  Jeong-Yun Lee ,  Shi Ii Quan ,  Sug-Hyun Sung

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device and method of fabricating the device, includes forming a fin-type active pattern that projects above a field insulating layer and forming a dummy gate structure that includes an epitaxial growth prevention layer to suppress nodule formation.

Abstract translation: 一种制造该器件的半导体器件和方法，包括形成在场绝缘层上方突出的鳍状有源图案，并形成包含外延生长防止层的虚拟栅极结构，以抑制结核形成。

公开(公告)号：US09608054B2

公开(公告)日：2017-03-28

申请号：US14933537

申请日：2015-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chongkwang Chang ,  Youngjoon Moon ,  Duck-nam Kim ,  Yeong-Jong Jeong

IPC: H01L29/04 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/04 ,  H01L21/28247 ,  H01L21/32137 ,  H01L21/32138 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4232 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern sequentially being stacked on the semiconductor substrate, a gate pattern including poly semiconductor and disposed on the metal-containing pattern, and a protective layer disposed on the gate pattern, wherein the protective layer includes oxide, nitride and/or oxynitride of the poly semiconductor.

公开(公告)号：US09419072B2

公开(公告)日：2016-08-16

申请号：US13915284

申请日：2013-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chongkwang Chang ,  Youngjoon Moon ,  Duck-nam Kim ,  Yeong-Jong Jeong

IPC: H01L21/336 ,  H01L29/04 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L29/04 ,  H01L21/28247 ,  H01L21/32137 ,  H01L21/32138 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4232 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern sequentially being stacked on the semiconductor substrate, a gate pattern including poly semiconductor and disposed on the metal-containing pattern, and a protective layer disposed on the gate pattern, wherein the protective layer includes oxide, nitride and/or oxynitride of the poly semiconductor.

公开(公告)号：US20160056259A1

公开(公告)日：2016-02-25

申请号：US14933537

申请日：2015-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chongkwang Chang ,  Youngjoon Moon ,  Duck-nam Kim ,  Yeong-Jong Jeong

IPC: H01L29/51 ,  H01L29/423

CPC classification number: H01L29/04 ,  H01L21/28247 ,  H01L21/32137 ,  H01L21/32138 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4232 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern sequentially being stacked on the semiconductor substrate, a gate pattern including poly semiconductor and disposed on the metal-containing pattern, and a protective layer disposed on the gate pattern, wherein the protective layer includes oxide, nitride and/or oxynitride of the poly semiconductor.

公开(公告)号：US09972717B2

公开(公告)日：2018-05-15

申请号：US15228421

申请日：2016-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong-Jong Jeong ,  Jeong-Yun Lee ,  Geo-Myung Shin ,  Dong-Suk Shin ,  Si-Hyung Lee ,  Seo-Jin Jeong

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/41 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device comprises a first multi-channel active pattern which is defined by a field insulating layer, extends along a first direction, and includes a first portion and a second portion; a gate electrode which extends along a second direction different from the first direction and is formed on the first portion; and a first source/drain region which is formed around the second portion protruding further upward than a top surface of the field insulating layer and contacts the field insulating layer, wherein the second portion is disposed on both sides of the first portion in the first direction and is more recessed than the first portion, a top surface of the first portion and a top surface of the second portion protrude further upward than the top surface of the field insulating layer, and a profile of sidewalls of the second portion is continuous.

公开(公告)号：US20160141381A1

公开(公告)日：2016-05-19

申请号：US14816568

申请日：2015-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kook-Tae KIM ,  Ho-Sung Son ,  Geo-Myung Shin ,  Dong-Suk Shin ,  Si-Hyung Lee ,  Ji-Hye Yi ,  Sung-Hoon Jung ,  Yeong-Jong Jeong

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor devices and methods for fabricating the same are provided. The semiconductor devices include a fin active pattern formed to project from a substrate, a gate electrode formed to cross the fin active pattern on the substrate, a gate spacer formed on a side wall of the gate electrode and having a low dielectric constant and an elevated source/drain formed on both sides of the gate electrode on the fin active pattern. The gate spacer includes first, second and third spacers that sequentially come in contact with each other in a direction in which the gate spacer goes out from the gate electrode, and a carbon concentration of the second spacer is lower than carbon concentrations of the first and third spacers.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括从衬底突出形成的鳍状有源图案，形成为跨越衬底上的鳍状活性图案的栅极电极，形成在栅电极的侧壁上并具有低介电常数和升高的栅极间隔 源极/漏极形成在鳍状物图案上的栅电极的两侧。 栅极间隔物包括在栅极间隔物从栅电极出来的方向上依次相互接触的第一，第二和第三间隔物，第二间隔物的碳浓度低于第一和第二间隔物的碳浓度， 第三间隔物。

公开(公告)号：US09318575B2

公开(公告)日：2016-04-19

申请号：US14313039

申请日：2014-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong-Jong Jeong ,  Jeong-Yun Lee ,  Shi Li Quan

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of forming a semiconductor device includes forming a gate structure including a polysilicon gate and forming a capping spacer on a side surface of the gate structure to prevent parasitic epitaxial growth on the side surface of the polysilicon gate.

Abstract translation: 一种形成半导体器件的方法包括在栅极结构的侧表面上形成包括多晶硅栅极并形成封盖间隔物的栅极结构，以防止多晶硅栅极的侧表面上的寄生外延生长。

公开(公告)号：US09263521B2

公开(公告)日：2016-02-16

申请号：US14713349

申请日：2015-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong-Jong Jeong ,  Jeong-Yun Lee ,  Shi Li Quan ,  Dong-Suk Shin ,  Si-Hyung Lee

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L27/08 ,  H01L27/092 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/41758 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7851

Abstract: Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin. The method may also include forming a first recess in the fin having a first width and a first depth and forming a second recess in the first recess having a second width that is less than the first width and having a second depth that is greater than the first depth. The method may further include forming a source/drain region in the first and second recesses.