公开(公告)号：US20220157723A1

公开(公告)日：2022-05-19

申请号：US17159972

申请日：2021-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saehan Park ,  Hoonseok Seo ,  Jeonghyuk Yim ,  Ki-il Kim ,  Gil Hwan Son

IPC: H01L23/528 ,  H01L27/06 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L21/822

Abstract: Provided is a semiconductor architecture including a carrier substrate, a landing pad included in the carrier substrate, a first semiconductor device provided on a first surface of the carrier substrate, the first semiconductor device including a first component provided on the landing pad, and a second semiconductor device provided on a second surface of the carrier substrate, a second component protruding from the second semiconductor device being provided on the landing pad.

公开(公告)号：US20230411294A1

公开(公告)日：2023-12-21

申请号：US18457000

申请日：2023-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Saehan PARK ,  Hoonseok Seo ,  Jeonghyuk Yim ,  Ki-il Kim ,  Gil Hwan Son

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/822 ,  H01L23/48 ,  H01L23/00 ,  H01L27/06

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L24/05 ,  H01L27/0694 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05176

Abstract: Provided is a semiconductor architecture including a carrier substrate, a landing pad included in the carrier substrate, a first semiconductor device provided on a first surface of the carrier substrate, the first semiconductor device including a first component provided on the landing pad, and a second semiconductor device provided on a second surface of the carrier substrate, a second component protruding from the second semiconductor device being provided on the landing pad.

公开(公告)号：US10038093B2

公开(公告)日：2018-07-31

申请号：US15223332

申请日：2016-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sug-Hyun Sung ,  Jung-gun You ,  Gi-gwan Park ,  Ki-il Kim

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/7843 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7854

Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.

公开(公告)号：US10707348B2

公开(公告)日：2020-07-07

申请号：US16587227

申请日：2019-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sug-Hyun Sung ,  Jung-gun You ,  Gi-gwan Park ,  Ki-il Kim

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L21/762

Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.

公开(公告)号：US10461189B2

公开(公告)日：2019-10-29

申请号：US16028918

申请日：2018-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sug-Hyun Sung ,  Jung-gun You ,  Gi-gwan Park ,  Ki-il Kim

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/762

Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.

公开(公告)号：US12255099B2

公开(公告)日：2025-03-18

申请号：US17590863

申请日：2022-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gunho Jo ,  Ki-il Kim ,  Byounghak Hong

IPC: H01L21/822 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Methods of forming a plurality of transistor stacks are provided. A method of forming a plurality of transistor stacks includes etching a plurality of nanosheets, using a plurality of spacers that are on sidewalls of a plurality of semiconductor fins as an etch mask, to provide a plurality of spaced-apart nanosheet stacks that each have at least one of the semiconductor fins thereon.

公开(公告)号：US12224314B2

公开(公告)日：2025-02-11

申请号：US17402214

申请日：2021-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gunho Jo ,  Ki-il Kim ,  Byounghak Hong ,  Kang-ill Seo

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A multi-stack semiconductor device includes: a substrate; and a plurality of multi-stack transistor structures arranged on the substrate in a channel width direction, wherein the multi-stack transistor structure include at least one lower transistor structure and at least one upper transistor structure stacked above the lower transistor structure, wherein the lower and upper transistor structures include at least one channel layer as a current channel, wherein the lower transistor structures of at least two multi-stack transistor structures have different channel-layer widths.

公开(公告)号：US11769728B2

公开(公告)日：2023-09-26

申请号：US17159972

申请日：2021-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saehan Park ,  Hoonseok Seo ,  Jeonghyuk Yim ,  Ki-il Kim ,  Gil Hwan Son

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/822 ,  H01L23/48 ,  H01L23/00 ,  H01L27/06

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L24/05 ,  H01L27/0694 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05176

Abstract: Provided is a semiconductor architecture including a carrier substrate, a landing pad included in the carrier substrate, a first semiconductor device provided on a first surface of the carrier substrate, the first semiconductor device including a first component provided on the landing pad, and a second semiconductor device provided on a second surface of the carrier substrate, a second component protruding from the second semiconductor device being provided on the landing pad.

公开(公告)号：US20230133731A1

公开(公告)日：2023-05-04

申请号：US17590863

申请日：2022-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gunho Jo ,  Ki-il Kim ,  Byounghak Hong

IPC: H01L21/822 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/66

Abstract: Methods of forming a plurality of transistor stacks are provided. A method of forming a plurality of transistor stacks includes etching a plurality of nanosheets, using a plurality of spacers that are on sidewalls of a plurality of semiconductor fins as an etch mask, to provide a plurality of spaced-apart nanosheet stacks that each have at least one of the semiconductor fins thereon.

公开(公告)号：US09853783B2

公开(公告)日：2017-12-26

申请号：US13631004

申请日：2012-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youn-Sun Kim ,  Hyo-Jin Lee ,  Joon-Young Cho ,  Ki-il Kim ,  Ju-Ho Lee

IPC: H04L5/00 ,  H04L1/02 ,  H04L25/02 ,  H04B7/024

CPC classification number: H04L5/0048 ,  H04B7/024 ,  H04L1/02 ,  H04L25/0224

Abstract: An apparatus and method for transmitting and receiving a signal in a Distributed Antenna System (DAS) is provided. A method for determining an initial state in a DAS includes receiving a value through high-level signalling and determining an initial state based on the value, in which the value includes a value in which is set an initial state of a scrambling sequence, which differs according to a transmission point.