公开(公告)号：US11956937B2

公开(公告)日：2024-04-09

申请号：US16751460

申请日：2020-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Il Kim ,  Jung-Gun You ,  Gi-Gwan Park

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/105 ,  H01L29/78 ,  H10B10/00

CPC classification number: H10B10/12 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/105 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7854

Abstract: A semiconductor device can include a field insulating film on a substrate and a fin-type pattern of a particular material, on the substrate, having a first sidewall and an opposing second sidewall. The fin-type pattern can include a first portion of the fin-type pattern that protrudes from an upper surface of the field insulating film and a second portion of the fin-type pattern disposed on the first portion. A third portion of the fin-type pattern can be disposed on the second portion where the third portion can be capped by a top rounded surface of the fin-type pattern and the first sidewall can have an undulated profile that spans the first, second and third portions.

公开(公告)号：US10186615B2

公开(公告)日：2019-01-22

申请号：US15889803

申请日：2018-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Soo Kim ,  Gi-Gwan Park ,  Song-E Kim ,  Koung-Min Ryu ,  Sun-Ki Min

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417

Abstract: A semiconductor device is provided which includes a first fin-type pattern including a first side surface and a second side surface opposite to each other, a first trench of a first depth adjacent to the first side surface, a second trench of a second depth adjacent to the second side surface. The second depth differs from the first depth, and a first field insulating film partially fills the first trench and a second field insulating film partially fills the second trench. The first fin-type pattern has a lower portion, and an upper portion having a narrower width than the lower portion, and has a first stepped portion on a boundary between the upper portion and the lower portion. The first field insulating film includes a first lower field insulating film in contact with the lower portion, and a first upper field insulating film in contact with the upper portion.

公开(公告)号：US10141312B2

公开(公告)日：2018-11-27

申请号：US15296703

申请日：2016-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin Jeon ,  Young-Gun Ko ,  Gi-Gwan Park ,  Je-Min Yoo

IPC: H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238

Abstract: Semiconductor devices are provided. A semiconductor device includes a first insulating material in a first fin. The semiconductor device includes a second insulating material in a second fin. The first and second insulating materials have different respective sizes. For example, in some embodiments, the first and second insulating materials have different respective widths and/or depths in the first and second fins, respectively.

公开(公告)号：US10128155B2

公开(公告)日：2018-11-13

申请号：US15831480

申请日：2017-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongkuk Jeong ,  Gi-Gwan Park

IPC: H01L27/11 ,  H01L21/8234 ,  H01L21/311 ,  H01L27/088 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092

Abstract: An integrated circuit device includes: a first fin-type active region in a first area of a substrate, the first fin-type active region having a first recess filled with a first source/drain region; a first device isolation layer covering both lower sidewalls of the first fin-type active region; a second fin-type active region in a second area of the substrate, the second fin-type active region having a second recess filled with a second source/drain region; a second device isolation layer covering both lower sidewalls of the second fin-type active region; and a fin insulating spacer on the first device isolation layer, the fin insulating spacer covering a sidewall of the first fin-type active region under the first source/drain region.

公开(公告)号：US09917174B2

公开(公告)日：2018-03-13

申请号：US15442871

申请日：2017-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Uk Jang ,  Gi-Gwan Park ,  Ho-Sung Son ,  Dong-Suk Shin

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/265 ,  H01L21/26506 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: In a method of manufacturing a semiconductor device, an isolation pattern may be formed on a substrate to define a plurality of active patterns. The active patterns may protrude from the isolation pattern. A preliminary polysilicon layer may be formed on the active patterns to fill a gap between adjacent ones of the active patterns. Ions having no conductivity may be implanted into the preliminary polysilicon layer to form a polysilicon layer having no void. The active patterns maintain their crystalline state during the implanting of the ions. The polysilicon layer may be patterned to form a dummy gate structure on the active pattern. A source/drain region may be formed at an upper portion of the active patterns adjacent to sides of the dummy gate structure.

公开(公告)号：US09875938B2

公开(公告)日：2018-01-23

申请号：US15356821

申请日：2016-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongkuk Jeong ,  Gi-Gwan Park

IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/311 ,  H01L27/088 ,  H01L27/11

CPC classification number: H01L21/823431 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/785

Abstract: An integrated circuit device includes: a first fin-type active region in a first area of a substrate, the first fin-type active region having a first recess filled with a first source/drain region; a first device isolation layer covering both lower sidewalls of the first fin-type active region; a second fin-type active region in a second area of the substrate, the second fin-type active region having a second recess filled with a second source/drain region; a second device isolation layer covering both lower sidewalls of the second fin-type active region; and a fin insulating spacer on the first device isolation layer, the fin insulating spacer covering a sidewall of the first fin-type active region under the first source/drain region.

公开(公告)号：US09711504B2

公开(公告)日：2017-07-18

申请号：US15155744

申请日：2016-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gun You ,  Ki-Il Kim ,  Gi-Gwan Park ,  Sug-Hyun Sung ,  Myung-Yoon Um

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7854

Abstract: A semiconductor device includes a substrate including a first trench, a first fin pattern on the substrate that is defined by the first trench, a gate electrode on the substrate, and a field insulating layer on the substrate. The first fin pattern includes an upper part on a lower part. The first fin pattern includes a first sidewall and a second sidewall opposite each other. The first sidewall is concave along the lower part of the first fin pattern. The second sidewall is tilted along the lower part of the first fin pattern. The field insulating layer surrounds the lower part of the first fin pattern. The gate electrode surrounds the upper part of the first fin pattern.

公开(公告)号：US20170084616A1

公开(公告)日：2017-03-23

申请号：US15213533

申请日：2016-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Il Kim ,  Jung-Gun You ,  Gi-Gwan Park

IPC: H01L27/11 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L27/1104 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7854

Abstract: A semiconductor device can include a field insulating film on a substrate and a fin-type pattern of a particular material, on the substrate, having a first sidewall and an opposing second sidewall. The fin-type pattern can include a first portion of the fin-type pattern that protrudes from an upper surface of the field insulating film and a second portion of the fin-type pattern disposed on the first portion. A third portion of the fin-type pattern can be disposed on the second portion where the third portion can be capped by a top rounded surface of the fin-type pattern and the first sidewall can have an undulated profile that spans the first, second and third portions.

公开(公告)号：US11069685B2

公开(公告)日：2021-07-20

申请号：US16453721

申请日：2019-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Chan Suh ,  Gi-Gwan Park ,  Dong-Woo Kim ,  Dong-Suk Shin

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

公开(公告)号：US10796919B2

公开(公告)日：2020-10-06

申请号：US15287268

申请日：2016-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hyuk Kim ,  Gi-Gwan Park ,  Tae-Young Kim ,  Dong-Suk Shin

IPC: H01L21/3065 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L29/78 ,  H01L29/165 ,  H01L29/161

Abstract: Methods for fabricating semiconductor devices include forming a fin-type pattern protruding on a substrate, forming a gate electrode intersecting the fin-type pattern, forming a first recess adjacent to the gate electrode and within the fin-type pattern by using dry etching, forming a second recess by treating a surface of the first recess with a surface treatment process including a deposit process and an etch process, and forming an epitaxial pattern in the second recess.