公开(公告)号：US10720491B2

公开(公告)日：2020-07-21

申请号：US16419153

申请日：2019-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Ho Yoon ,  Won Chul Lee ,  Sung Yeon Kim ,  Jae Hong Park ,  Chan Hoon Park ,  Yong Moon Jang ,  Je Woo Han

IPC: H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L49/02 ,  H01L21/033 ,  H01L21/3205 ,  H01L21/8242 ,  H01L21/306

Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole.

公开(公告)号：US10756091B2

公开(公告)日：2020-08-25

申请号：US16279360

申请日：2019-02-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Ung Pak ,  Won Chul Lee

IPC: H01L27/108 ,  H01L27/11 ,  G11C11/416 ,  H01L21/285 ,  G11C7/12 ,  G11C11/56 ,  H01L49/02 ,  H01L27/112 ,  G11C5/02 ,  G11C11/403 ,  G11C11/412

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate which includes a cell region including first and second regions, and a peri region more adjacent to the second region than adjacent to the first region, first and second lower electrodes disposed in the first and second regions, respectively, first and second lower support patterns disposed on outer walls of the first and second lower electrodes, respectively, an upper support pattern disposed on outer walls of the first and second lower electrodes, and being on and spaced apart from the first and second lower support patterns, a dielectric layer disposed on surfaces of the first and second lower electrodes, the first and second lower support patterns, and the upper support pattern, and an upper electrode disposed on a surface of the dielectric layer, wherein thickness of the first lower support pattern is smaller than thickness of the second lower support pattern.

公开(公告)号：US20180331112A1

公开(公告)日：2018-11-15

申请号：US16043619

申请日：2018-07-24

Applicant: SAMSUNG ELECTRONICS CO, LTD

Inventor： YE RAM KIM ,  Won Chul Lee

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10852 ,  H01L27/10814 ,  H01L28/56 ,  H01L28/87 ,  H01L28/91

Abstract: A semiconductor device includes a substrate, a plurality of lower electrodes disposed on the substrate and are repeatedly arranged in a first direction and in a second direction that crosses the first direction, and a first electrode support contacting a sidewall of at least one of the lower electrodes. The first electrode support includes a first support region including a first opening and a second support region disposed at a border of the first support region. An outer sidewall of the first electrode support includes a first sidewall extending in the first direction, a second sidewall extending in the second direction, and a connecting sidewall connecting the first and second sidewalls. The second support region includes the connecting sidewall. In a first portion of the second support region, a width of the first portion of the second support region decreases in a direction away from the first support region.

公开(公告)号：US10607997B2

公开(公告)日：2020-03-31

申请号：US16543216

申请日：2019-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ye Ram Kim ,  Won Chul Lee

IPC: H01L27/108 ,  H01L49/02

Abstract: A semiconductor device includes a substrate, a plurality of lower electrodes disposed on the substrate and are repeatedly arranged in a first direction and in a second direction that crosses the first direction, and a first electrode support contacting a sidewall of at least one of the lower electrodes. The first electrode support includes a first support region including a first opening and a second support region disposed at a border of the first support region. An outer sidewall of the first electrode support includes a first sidewall extending in the first direction, a second sidewall extending in the second direction, and a connecting sidewall connecting the first and second sidewalls. The second support region includes the connecting sidewall. In a first portion of the second support region, a width of the first portion of the second support region decreases in a direction away from the first support region.

公开(公告)号：US11842076B2

公开(公告)日：2023-12-12

申请号：US17478449

申请日：2021-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won Chul Lee ,  Mun Seop Lim

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0653 ,  G06F3/0673

Abstract: A storage system includes a storage device and an overlap checker. The overlap checker receives I/O commands of the storage device, extracts characteristics of the received I/O commands, issues a first merge command including N first I/O commands among the I/O commands in response to the extracted characteristics, wherein ‘N’ is a natural number greater than 1. And each of the first I/O commands instructs operation on a position corresponding to an offset in a region of the storage device corresponding to a logical address, wherein the characteristics of the I/O commands include the logical address and the offset.

公开(公告)号：US20190189619A1

公开(公告)日：2019-06-20

申请号：US16279360

申请日：2019-02-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI UNG PAK ,  Won Chul Lee

IPC: H01L27/108 ,  G11C7/12 ,  H01L21/285 ,  H01L49/02 ,  G11C11/56 ,  H01L27/11 ,  H01L27/112 ,  G11C11/416

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate which includes a cell region including first and second regions, and a peri region more adjacent to the second region than adjacent to the first region, first and second lower electrodes disposed in the first and second regions, respectively, first and second lower support patterns disposed on outer walls of the first and second lower electrodes, respectively, an upper support pattern disposed on outer walls of the first and second lower electrodes, and being on and spaced apart from the first and second lower support patterns, a dielectric layer disposed on surfaces of the first and second lower electrodes, the first and second lower support patterns, and the upper support pattern, and an upper electrode disposed on a surface of the dielectric layer, wherein thickness of the first lower support pattern is smaller than thickness of the second lower support pattern.

公开(公告)号：US10319805B2

公开(公告)日：2019-06-11

申请号：US15626271

申请日：2017-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Ho Yoon ,  Won Chul Lee ,  Sung Yeon Kim ,  Jae Hong Park ,  Chan Hoon Park ,  Yong Moon Jang ,  Je Woo Han

IPC: H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L49/02 ,  H01L21/033 ,  H01L21/3205 ,  H01L21/8242 ,  H01L21/306

Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole.

公开(公告)号：US10304838B2

公开(公告)日：2019-05-28

申请号：US15722053

申请日：2017-10-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ye Ram Kim ,  Won Chul Lee

IPC: H01L27/108 ,  H01L29/94 ,  H01L23/64 ,  H01L21/768 ,  H01L49/02

Abstract: A semiconductor device and method of manufacturing are provided. The semiconductor device includes a substrate; first and second structures spaced apart from each other on the substrate in a first direction, the first structure including a first lower electrode and the second structure including a second lower electrode; a first supporter pattern disposed on the substrate to support the first and second structures, and including a first region that exposes portions of sidewalls of the first and second structures, and a second region that covers a second portion of the sidewalls; and a second supporter pattern disposed on the first supporter pattern to support the first and second structures, the second supporter pattern including a third region, the third region configured to expose portions of the first sidewall and the second sidewall, and a fourth region that covers a portion of the first and second sidewalls.

公开(公告)号：US20180166447A1

公开(公告)日：2018-06-14

申请号：US15677726

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Ung Pak ,  Won Chul Lee ,  Je Min Park

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10808 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/87 ,  H01L28/91

Abstract: A semiconductor device includes a substrate, first, second and third structures disposed on the substrate and spaced apart from one another in a first direction, wherein each of the first, second and third structures includes lower electrodes, and a supporter pattern supporting the first, second and third structures and including a first region and a second region, wherein the first region exposes first parts of sidewalls of the first, second and third structures, and the second region surrounds second parts of the sidewalls of the first, second and third structures. A first length of a sidewall of the supporter pattern between the first and second structures is greater than a first distance between the first and second structures. A second length of a sidewall of the supporter pattern between the second and third structures is greater than a second distance between the second and third structures.

公开(公告)号：US20230363149A1

公开(公告)日：2023-11-09

申请号：US18077419

申请日：2022-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： So Hyeon Bae ,  Won Chul Lee ,  Byeong Jun Bae

IPC: H01L29/94

CPC classification number: H01L27/10897 ,  H01L27/10814 ,  H01L27/10894

Abstract: A semiconductor memory device may include a substrate including a cell region and a peripheral region defined around the cell region, and a gate structure which may include sequentially stacked first, second, and third conductive layers including different materials, the first conductive layer including polysilicon. A capping layer may be on the third conductive layer, and a spacer may be on a sidewall of each of the first to third conductive layers and the capping layer. A first contact may extend through the capping layer and into the third conductive layer, with the first contact in contact with the second conductive layer, and separated from the first conductive layer. The first contact may include a first portion in the third conductive layer and a second portion in the capping layer. A width of the first portion may be greater than a width of the second portion in a horizontal direction.