公开(公告)号：US20230033091A1

公开(公告)日：2023-02-02

申请号：US17951910

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan Hoon Park ,  Jung Hwan Um ,  Jin Young Park ,  Ho Yong Park ,  Jin Young Bang ,  Jong Woo Sun ,  Sang Jean Jeon ,  Je Woo Han

IPC: H01J37/32 ,  H01L21/67

Abstract: A plasma processing apparatus may include a support configured to receive a substrate, a gas distribution plate (GDP) including a plurality of nozzles facing the support, a main splitter configured to supply a process gas, and an additional splitter configured to supply an acceleration gas or a deceleration gas. The plurality of nozzles may include a plurality of central nozzles, a plurality of outer nozzles, a plurality of middle nozzles configured to spray the process gas and the acceleration gas, a plurality of first nozzles, and a plurality of second nozzles.

公开(公告)号：US11018046B2

公开(公告)日：2021-05-25

申请号：US16559762

申请日：2019-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Woo Sun ,  Sung Moon Park ,  Je Woo Han ,  Kwang Nam Kim ,  Ho Chang Lee ,  Young Hoon Jeong ,  Masayuki Tomoyasu

IPC: H01L21/687 ,  H01L21/67 ,  H01J37/32

Abstract: A substrate processing apparatus including a process chamber; a susceptor in the process chamber; and an inner edge ring and an outer edge ring on the susceptor, wherein the inner edge ring includes a semiconductor, the outer edge ring includes an insulator, an upper surface of the outer edge ring is at a higher level than an upper surface of the inner edge ring, and the outer edge ring has an overhang extending onto the inner edge ring.

公开(公告)号：US11437264B2

公开(公告)日：2022-09-06

申请号：US17182613

申请日：2021-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Mo Sung ,  Jong Woo Sun ,  Je Woo Han ,  Chan Hoon Park ,  Seung Yoon Song ,  Seul Ha Myung

IPC: H01L21/68 ,  H01L21/683 ,  H01L21/67

Abstract: A semiconductor processing apparatus includes a chamber housing, an electrostatic chuck disposed in the chamber housing, the electrostatic chuck being configured to hold a semiconductor wafer, an edge ring surrounding the electrostatic chuck, the edge ring including a ring electrode disposed within the edge ring, and a ring voltage supply configured to supply a ring voltage to the ring electrode, the ring voltage having a non-sinusoidal periodic waveform, wherein each period of the non-sinusoidal periodic waveform comprises a positive voltage applied during a first time period and a negative voltage applied during a second time period, and wherein the negative voltage has a magnitude that increases during the second time period.

公开(公告)号：US10319805B2

公开(公告)日：2019-06-11

申请号：US15626271

申请日：2017-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Ho Yoon ,  Won Chul Lee ,  Sung Yeon Kim ,  Jae Hong Park ,  Chan Hoon Park ,  Yong Moon Jang ,  Je Woo Han

IPC: H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L49/02 ,  H01L21/033 ,  H01L21/3205 ,  H01L21/8242 ,  H01L21/306

Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole.

公开(公告)号：US10720491B2

公开(公告)日：2020-07-21

申请号：US16419153

申请日：2019-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Ho Yoon ,  Won Chul Lee ,  Sung Yeon Kim ,  Jae Hong Park ,  Chan Hoon Park ,  Yong Moon Jang ,  Je Woo Han

IPC: H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L49/02 ,  H01L21/033 ,  H01L21/3205 ,  H01L21/8242 ,  H01L21/306

Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole.

公开(公告)号：US20190304751A1

公开(公告)日：2019-10-03

申请号：US16118939

申请日：2018-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan Hoon Park ,  Jung Hwan Um ,  Jin Young Park ,  Ho Yong Park ,  Jin Young Bang ,  Jong Woo Sun ,  Sang Jean Jeon ,  Je Woo Han

IPC: H01J37/32 ,  H01L21/67

Abstract: A plasma processing apparatus may include a support configured to receive a substrate, a gas distribution plate (GDP) including a plurality of nozzles facing the support, a main splitter configured to supply a process gas, and an additional splitter configured to supply an acceleration gas or a deceleration gas. The plurality of nozzles may include a plurality of central nozzles, a plurality of outer nozzles, a plurality of middle nozzles configured to spray the process gas and the acceleration gas, a plurality of first nozzles, and a plurality of second nozzles.

公开(公告)号：US11837496B2

公开(公告)日：2023-12-05

申请号：US17324229

申请日：2021-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Woo Sun ,  Sung Moon Park ,  Je Woo Han ,  Kwang Nam Kim ,  Ho Chang Lee ,  Young Hoon Jeong ,  Masayuki Tomoyasu

IPC: H01L21/687 ,  H01L21/67 ,  H01J37/32

CPC classification number: H01L21/68735 ,  H01J37/3244 ,  H01J37/32532 ,  H01J37/32642 ,  H01L21/67069 ,  H01L21/6875

Abstract: A substrate processing apparatus including a process chamber; a susceptor in the process chamber; and an inner edge ring and an outer edge ring on the susceptor, wherein the inner edge ring includes a semiconductor, the outer edge ring includes an insulator, an upper surface of the outer edge ring is at a higher level than an upper surface of the inner edge ring, and the outer edge ring has an overhang extending onto the inner edge ring.

公开(公告)号：US11791194B2

公开(公告)日：2023-10-17

申请号：US17324229

申请日：2021-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Woo Sun ,  Sung Moon Park ,  Je Woo Han ,  Kwang Nam Kim ,  Ho Chang Lee ,  Young Hoon Jeong ,  Masayuki Tomoyasu

IPC: H01L21/687 ,  H01L21/67 ,  H01J37/32

CPC classification number: H01L21/68735 ,  H01J37/3244 ,  H01J37/32532 ,  H01J37/32642 ,  H01L21/67069 ,  H01L21/6875

Abstract: A substrate processing apparatus including a process chamber; a susceptor in the process chamber; and an inner edge ring and an outer edge ring on the susceptor, wherein the inner edge ring includes a semiconductor, the outer edge ring includes an insulator, an upper surface of the outer edge ring is at a higher level than an upper surface of the inner edge ring, and the outer edge ring has an overhang extending onto the inner edge ring.

公开(公告)号：US10964578B2

公开(公告)日：2021-03-30

申请号：US16401792

申请日：2019-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Mo Sung ,  Jong Woo Sun ,  Je Woo Han ,  Chan Hoon Park ,  Seung Yoon Song ,  Seul Ha Myung

IPC: H01L21/683 ,  H01L21/67

Abstract: A semiconductor processing apparatus includes a chamber housing, an electrostatic chuck disposed in the chamber housing, the electrostatic chuck being configured to hold a semiconductor wafer, an edge ring surrounding the electrostatic chuck, the edge ring including a ring electrode disposed within the edge ring, and a ring voltage supply configured to supply a ring voltage to the ring electrode, the ring voltage having a non-sinusoidal periodic waveform, wherein each period of the non-sinusoidal periodic waveform comprises a positive voltage applied during a first time period and a negative voltage applied during a second time period, and wherein the negative voltage has a magnitude that increases during the second time period.