中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.014 seconds)

    Nonvolatile memory devices and methods of forming same
    2.
    发明授权
    Nonvolatile memory devices and methods of forming same 有权

    公开(公告)号：US10153295B2

    公开(公告)日：2018-12-11

    申请号：US15613602

    申请日：2017-06-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woong-Seop Lee ,  Seokcheon Baek ,  Jinhyun Shin

    IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11575

    Abstract: A vertical NAND-type memory device includes a vertical stack of inter-gate insulating layers and gate electrodes arranged in an alternating sequence on an underlying substrate, which includes a cell array region and a contact region therein. At least one NAND-type channel structure is provided, which extends vertically through the vertical stack of inter-gate insulating layers and gate electrodes. An end sidewall of a first of the gate electrodes, which extends laterally over at least a portion of the contact region, has a vertical slope that is less steep than vertical slopes of end sidewalls of a first plurality of the gate electrodes extending between the first of the gate electrodes and the substrate.

    Nonvolatile memory devices and methods of forming same
    3.
    发明授权
    Nonvolatile memory devices and methods of forming same 有权

    公开(公告)号：US09704878B2

    公开(公告)日：2017-07-11

    申请号：US15252931

    申请日：2016-08-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woong-Seop Lee ,  Seokcheon Baek ,  Jinhyun Shin

    IPC: H01L21/70 ,  H01L27/11582 ,  H01L27/11556

    CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11575

    Abstract: A vertical NAND-type memory device includes a vertical stack of inter-gate insulating layers and gate electrodes arranged in an alternating sequence on an underlying substrate, which includes a cell array region and a contact region therein. At least one NAND-type channel structure is provided, which extends vertically through the vertical stack of inter-gate insulating layers and gate electrodes. An end sidewall of a first of the gate electrodes, which extends laterally over at least a portion of the contact region, has a vertical slope that is less steep than vertical slopes of end sidewalls of a first plurality of the gate electrodes extending between the first of the gate electrodes and the substrate.

    Three-dimensional semiconductor memory device
    4.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US10128266B2

    公开(公告)日：2018-11-13

    申请号：US15592030

    申请日：2017-05-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jung Hoon Lee ,  Keejeong Rho ,  Sejun Park ,  Jinhyun Shin ,  Dong-Sik Lee ,  Woong-Seop Lee

    IPC: H01L27/11582 ,  H01L23/528 ,  G11C16/08 ,  H01L27/11556 ,  H01L27/1157

    Abstract: A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.

    NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING SAME
    5.
    发明申请
    NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING SAME 有权

    公开(公告)号：US20170103996A1

    公开(公告)日：2017-04-13

    申请号：US15252931

    申请日：2016-08-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woong-Seop Lee ,  Seokcheon Baek ,  Jinhyun Shin

    IPC: H01L27/115

    CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11575

    Abstract: A vertical NAND-type memory device includes a vertical stack of inter-gate insulating layers and gate electrodes arranged in an alternating sequence on an underlying substrate, which includes a cell array region and a contact region therein. At least one NAND-type channel structure is provided, which extends vertically through the vertical stack of inter-gate insulating layers and gate electrodes. An end sidewall of a first of the gate electrodes, which extends laterally over at least a portion of the contact region, has a vertical slope that is less steep than vertical slopes of end sidewalls of a first plurality of the gate electrodes extending between the first of the gate electrodes and the substrate.

    NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING SAME
    6.
    发明申请
    NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING SAME 审中-公开

    公开(公告)号：US20170301688A1

    公开(公告)日：2017-10-19

    申请号：US15613602

    申请日：2017-06-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woong-Seop Lee ,  Seokcheon Baek ,  Jinhyun Shin

    IPC: H01L27/115

    CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11575

    Abstract: A vertical NAND-type memory device includes a vertical stack of inter-gate insulating layers and gate electrodes arranged in an alternating sequence on an underlying substrate, which includes a cell array region and a contact region therein. At least one NAND-type channel structure is provided, which extends vertically through the vertical stack of inter-gate insulating layers and gate electrodes. An end sidewall of a first of the gate electrodes, which extends laterally over at least a portion of the contact region, has a vertical slope that is less steep than vertical slopes of end sidewalls of a first plurality of the gate electrodes extending between the first of the gate electrodes and the substrate.

Patent Agency Ranking