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公开(公告)号：US12131789B2
公开(公告)日：2024-10-29
申请号：US17847545
申请日：2022-06-23
发明人： Junho Kim , Jinyoung Kim , Sehwan Park , Seoyoung Lee , Jisang Lee , Joonsuc Jang
CPC分类号： G11C16/3459 , G11C16/08 , G11C16/102 , G11C16/26 , G11C16/3404
摘要： Aggressor memory cells connected to one or more aggressor wordlines are grouped into aggressor cell groups by performing a read operation with respect to the aggressor wordlines based on one or more grouping read voltages, where the aggressor wordlines are adjacent to a selected wordline corresponding to a read address among wordlines of a memory block. Selected memory cells connected to the selected wordline are grouped into a selected cell groups respectively corresponding to the aggressor cell groups. Group read conditions respectively corresponding to the selected cell groups are determined and group read operations are performed with respect to the plurality of selected cell groups based on the group read conditions. The read errors are reduced by grouping the selected memory cells into the selected cell groups according to the change of operation environments.
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公开(公告)号：US20220093184A1
公开(公告)日：2022-03-24
申请号：US17324333
申请日：2021-05-19
发明人： Jisu Kim , Hyunggon Kim , Sangsoo Park , Joonsuc Jang , Minseok Kim
IPC分类号： G11C16/26 , H01L25/065 , H01L25/18 , H01L23/00 , G11C11/56 , G11C16/04 , G11C16/24 , G06F11/10
摘要： Provided is a storage device that performs a read operation by using a time interleaved sampling page buffer. The storage device controls a sensing point in time, when bit lines of even page buffer circuits are sensed, and a sensing point in time, when bit lines of odd page buffer circuits are sensed, with a certain time difference, and performs an Even Odd Sensing (EOS) operation in a stated order of even sensing and odd sensing. The storage device performs a two-step EOS operation and performs a main sensing operation on a selected memory cell according to a result of the two-step EOS operation.
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3.发明授权公开(公告)号：US11626171B2
公开(公告)日：2023-04-11
申请号：US17201828
申请日：2021-03-15
发明人： Joonsuc Jang , Hyunggon Kim , Sangbum Yun , Dongwook Kim , Kyungsoo Park , Sejin Baek
摘要： A method of programming a nonvolatile memory device includes performing a single-pulse program operation in a program loop, determining whether a condition is satisfied in the a program loop, and performing a multi-pulse program operation in a next program loop when the condition is satisfied. The single-pulse program operation includes applying a first program pulse and applying plural verification pulses, the multi-pulse program operation includes applying a second program pulse, applying a third program pulse, and applying plural verification pulses, and each of the second program pulse and the third program pulse has a level lower than a level of the first program pulse.
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公开(公告)号：US11574692B2
公开(公告)日：2023-02-07
申请号：US17359688
申请日：2021-06-28
发明人： Kwangho Choi , Jin-Young Kim , Se Hwan Park , Il Han Park , Ji-Sang Lee , Joonsuc Jang
IPC分类号： G11C16/34 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , H01L25/065 , H01L25/18 , H01L23/00
摘要： A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.
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公开(公告)号：US11990189B2
公开(公告)日：2024-05-21
申请号：US17839253
申请日：2022-06-13
发明人： Younghwi Yang , Joonsuc Jang
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/10 , H01L24/08 , H01L25/0657 , H01L25/18 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
摘要： A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings that are divided into a plurality of stacks disposed in the vertical direction, and each of the plurality of stacks includes at least one dummy word-line. The control circuit controls a program operation by applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period and by reducing a voltage level of a dummy voltage applied to the at least one dummy word-line of at least one upper stack from among the plurality of stacks during the program execution period. The at least one upper stack is disposed at a higher position than a selected stack in the vertical direction and the selected stack from among the plurality of stacks includes the selected word-line.
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公开(公告)号：US11862273B2
公开(公告)日：2024-01-02
申请号：US18068337
申请日：2022-12-19
发明人： Sehwan Park , Jinyoung Kim , Youngdeok Seo , Dongmin Shin , Joonsuc Jang , Sungmin Joe
CPC分类号： G11C29/42 , G11C16/102 , G11C16/26 , G11C29/12015 , G11C29/18 , G11C29/4401 , G11C2029/1202 , G11C2029/1204 , G11C2029/1802
摘要： A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.
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7.发明授权公开(公告)号：US11594293B2
公开(公告)日：2023-02-28
申请号：US17336910
申请日：2021-06-02
发明人： Garam Kim , Hyunggon Kim , Jisang Lee , Joonsuc Jang , Wontaeck Jung
摘要： A memory device includes a memory cell array including a plurality of memory cells; a voltage generator configured to generate voltages used for a program operation and a verify operation for the memory cells; and control logic configured to perform a plurality of program loops while writing data to the memory cell array, such that first to N-th (e.g., N>=1) program loops including a program operation and a verify operation are performed and at least two program loops in which the verify operation is skipped are performed when a pass/fail determination of the program operation in the N-th program loop indicates a pass.
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公开(公告)号：US20230154552A1
公开(公告)日：2023-05-18
申请号：US17847545
申请日：2022-06-23
发明人： Junho Kim , Jinyoung Kim , Sehwan Park , Seoyoung Lee , Jisang Lee , Joonsuc Jang
CPC分类号： G11C16/3459 , G11C16/3404 , G11C16/102 , G11C16/26 , G11C16/08
摘要： Aggressor memory cells connected to one or more aggressor wordlines are grouped into aggressor cell groups by performing a read operation with respect to the aggressor wordlines based on one or more grouping read voltages, where the aggressor wordlines are adjacent to a selected wordline corresponding to a read address among wordlines of a memory block. Selected memory cells connected to the selected wordline are grouped into a selected cell groups respectively corresponding to the aggressor cell groups. Group read conditions respectively corresponding to the selected cell groups are determined and group read operations are performed with respect to the plurality of selected cell groups based on the group read conditions. The read errors are reduced by grouping the selected memory cells into the selected cell groups according to the change of operation environments.
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9.发明授权公开(公告)号：US11309032B2
公开(公告)日：2022-04-19
申请号：US17077200
申请日：2020-10-22
发明人： Joonsuc Jang
IPC分类号： G11C16/10 , G06F3/06 , G06F11/10 , G11C11/56 , G11C16/08 , G11C16/26 , G11C16/34 , G11C16/04
摘要： An operating method of a memory system includes preprogramming multi-page data of a memory controller to a nonvolatile memory device, generating a state group code based on multi-bit data of the multi-page data, and each state group data of the state group code having less number of bits than corresponding multi-bit data, detecting sudden power-off occurring after the preprogramming, backing up, in response to the detecting of the sudden power-off occurring, the state group code to the nonvolatile memory device, recovering, after power is recovered from the sudden power-off, the multi-page data from the nonvolatile memory device, based on the state group code, reprogramming the multi-page data to the nonvolatile memory device, and reprogramming, in response to the detecting of the sudden power-off not occurring, the multi-page data of the memory controller to the nonvolatile memory device.
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10.发明申请公开(公告)号：US20210158874A1
公开(公告)日：2021-05-27
申请号：US17077200
申请日：2020-10-22
发明人： Joonsuc Jang
摘要： An operating method of a memory system includes preprogramming multi-page data of a memory controller to a nonvolatile memory device, generating a state group code based on multi-bit data of the multi-page data, and each state group data of the state group code having less number of bits than corresponding multi-bit data, detecting sudden power-off occurring after the preprogramming, backing up, in response to the detecting of the sudden power-off occurring, the state group code to the nonvolatile memory device, recovering, after power is recovered from the sudden power-off, the multi-page data from the nonvolatile memory device, based on the state group code, reprogramming the multi-page data to the nonvolatile memory device, and reprogramming, in response to the detecting of the sudden power-off not occurring, the multi-page data of the memory controller to the nonvolatile memory device.
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