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1.发明授权公开(公告)号：US10971247B2
公开(公告)日：2021-04-06
申请号：US16283650
申请日：2019-02-22
发明人： Kyung-Ryun Kim , Yoon-Na Oh , Hyung-Jin Kim , Hui-Kap Yang , Jang-Woo Ryu
摘要： A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.
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公开(公告)号：US09921749B2
公开(公告)日：2018-03-20
申请号：US14743458
申请日：2015-06-18
发明人： Kyung-Ryun Kim , Joon-Suc Jang
CPC分类号： G06F3/061 , G06F3/0653 , G06F3/0673 , G06F12/0246 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/349
摘要： A method of operating a memory system, including a memory device, includes managing program order information of the memory device based on a program order stamp (POS) indicating a relative temporal relationship between program operations of a plurality of memory groups that are included in the memory device. The method includes generating a first mapping table that stores a read voltage offset and an upper POS corresponding to the read voltage offset, by using a plurality of voltage levels that are sequentially decreased or reduced, and generating a second mapping table that stores the read voltage offset and a lower POS corresponding to the read voltage offset, by using a plurality of voltage levels that are sequentially increased. A read voltage for performing a read operation on the memory device is variably determined based on the first and second mapping tables and the program order information.
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3.发明授权公开(公告)号：US10706911B1
公开(公告)日：2020-07-07
申请号：US16156052
申请日：2018-10-10
发明人： Young-Hun Seo , Kyung-Ryun Kim
IPC分类号： G11C7/00 , G11C11/4091 , G11C11/56
摘要： A sense amplifier includes a first sense amplification circuit electrically connected between a bit line, to which a multi-bit memory cell is also connected, and a complementary bit line. The first sense amplification circuit is configured to sense a least significant bit (LSB) of 2-bit data in the memory cell and latch the LSB in a first sensing bit line pair. A second sense amplification circuit is provided, which is configured to sense a most significant bit (MSB) of the 2-bit data and latch the MSB in a second sensing bit line pair. A switching circuit is provided, which is configured to selectively connect between bit lines of the first sensing bit line pair and bit lines of the second sensing bit line pair.
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4.发明授权Method and device for optimizing log likelihood ratio (LLR) used for nonvolatile memory device and for correcting errors in nonvolatile memory device 有权用于优化用于非易失性存储器件的对数似然比（LLR）和用于校正非易失性存储器件中的错误的方法和装置公开(公告)号：US09502137B2
公开(公告)日：2016-11-22
申请号：US14205482
申请日：2014-03-12
发明人： Sang-Yong Yoon , Kyung-Ryun Kim , Jin-Young Chun
CPC分类号： G11C29/50004 , G06F11/1048 , G06F11/1068 , G11C11/56 , G11C16/34 , G11C29/026 , G11C29/028 , H03M13/3927
摘要： In a method of optimizing a log likelihood ratio (LLR) used to correct errors related to data stored in a nonvolatile memory device, variation of threshold voltage distribution for a plurality of memory cells included in the nonvolatile memory device is monitored, and the LLR for the memory cells is updated based on a monitoring result. Although the characteristics of the memory cells are deteriorated, the LLR is continuously maintained to the optimal value.
摘要翻译： 在优化用于校正与存储在非易失性存储器件中的数据有关的误差的对数似然比（LLR）的方法中，监视非易失性存储器件中包括的多个存储器单元的阈值电压分布的变化，并且LLR用于 基于监视结果来更新存储器单元。 虽然存储单元的特性恶化，但是LLR连续地保持在最佳值。
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5.发明授权公开(公告)号：US11626185B2
公开(公告)日：2023-04-11
申请号：US17723200
申请日：2022-04-18
发明人： Kyung-Ryun Kim , Yoon-Na Oh , Hyung-Jin Kim , Hui-Kap Yang , Jang-Woo Ryu
摘要： A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.
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公开(公告)号：US09501343B2
公开(公告)日：2016-11-22
申请号：US14697381
申请日：2015-04-27
发明人： Kyung-Ryun Kim
CPC分类号： G06F11/076 , G06F11/073 , G06F11/1048 , G11C16/10
摘要： A method of operating a non-volatile memory device including first buffer memory cells and main memory cells, where the first buffer memory cells store first data, the main memory cells store second data, which is read from the first buffer memory cells, or recovered first data, which is recovered from the second data through a correction process, includes reading data, which is stored in sample buffer memory cells included in the first buffer memory cells, as sample data when an accumulated number of read commands, which are executed on the non-volatile memory device, reaches a reference value. The method includes counting the number of errors included in the sample data based an error correction code, and determining whether the main memory cells store the second data or the recovered first data based on the number of the errors relative to the first threshold value.
摘要翻译： 一种操作包括第一缓冲存储器单元和主存储单元的非易失性存储器件的方法，其中第一缓冲存储器单元存储第一数据，主存储单元存储从第一缓冲存储器单元读取的第二数据，或恢复 通过校正处理从第二数据中恢复的第一数据包括当累积的读取命令数量被执行时将存储在第一缓冲存储器单元中的采样缓冲存储单元中的读取数据作为采样数据， 非易失性存储器件达到参考值。 该方法包括基于错误校正码对包含在样本数据中的错误数进行计数，并且基于相对于第一阈值的错误数量来确定主存储器单元是否存储第二数据还是恢复的第一数据。
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公开(公告)号：US11194657B2
公开(公告)日：2021-12-07
申请号：US16823443
申请日：2020-03-19
发明人： Sang-Uhn Cha , Kyung-Ryun Kim , Young-Hun Seo
IPC分类号： G06F11/10 , G11C29/52 , G11C11/4093 , G11C11/4096 , H01L25/065 , G11C11/407 , G11C5/04
摘要： A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of bank arrays, and each of the bank arrays includes dynamic memory cells. The control logic circuit generates a first control signal to control the I/O gating circuit and a second control signal to control the ECC engine, in response to an access address and a command. The control logic circuit controls the ECC engine to perform s-bit ECC encoding on a write data to be stored in a first page of at least one bank array, in response to a first command, and controls the ECC engine to perform t-bit ECC decoding on a first codeword read from the first page, in response to a second command.
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8.发明授权公开(公告)号：US10854277B2
公开(公告)日：2020-12-01
申请号：US16888006
申请日：2020-05-29
发明人： Young-Hun Seo , Kyung-Ryun Kim
IPC分类号： G11C7/00 , G11C11/4091 , G11C11/56
摘要： A sense amplifier includes a first sense amplification circuit electrically connected between a bit line, to which a multi-bit memory cell is also connected, and a complementary bit line. The first sense amplification circuit is configured to sense a least significant bit (LSB) of 2-bit data in the memory cell and latch the LSB in a first sensing bit line pair. A second sense amplification circuit is provided, which is configured to sense a most significant bit (MSB) of the 2-bit data and latch the MSB in a second sensing bit line pair. A switching circuit is provided, which is configured to selectively connect between bit lines of the first sensing bit line pair and bit lines of the second sensing bit line pair.
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公开(公告)号：US10692582B2
公开(公告)日：2020-06-23
申请号：US16130544
申请日：2018-09-13
发明人： Kyung-Ryun Kim
摘要： A semiconductor memory device a memory cell array and a repair control circuit. The memory cell array including a normal cell region and a redundancy cell region, the normal cell region including a plurality of normal region groups, and redundancy cell region configured to replace failed memory cells of the normal cell region. The repair control circuit configured to, determine a target normal region group from among the plurality of normal region groups based on an input address, extract target fail addresses from among a plurality of fail addresses based on the target normal region group, and control a repair operation based on the target fail addresses and the input address.
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公开(公告)号：US09858014B2
公开(公告)日：2018-01-02
申请号：US14666476
申请日：2015-03-24
发明人： Kyung-Ryun Kim
IPC分类号： G06F3/06
CPC分类号： G06F3/0679 , G06F3/061 , G06F3/0659
摘要： A method of operating a memory system includes managing program order information of the memory device based on program order stamps (POSs) indicating relative temporal relationships between program operations performed in relation to a plurality of memory groups included in the memory device, and controlling operations directed to the plurality of memory groups in response to the program order information.
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