公开(公告)号：US20230038363A1

公开(公告)日：2023-02-09

申请号：US17848844

申请日：2022-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Chu OH ,  Byungchul JANG ,  Junyeong SEOK ,  Younggul SONG ,  Joonsung LIM

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: Provided is a three-dimensional storage device using wafer-to-wafer bonding. A storage device includes a first chip including a first substrate and a peripheral circuit region including a first control logic circuit configured to control operation modes of the non-volatile memory device and a second chip including a second substrate and three-dimensional arrays of non-volatile memory cells. The second chip may be vertically stacked on the first chip so that a first surface of the first substrate faces a first surface of the second substrate, and a second control logic circuit is configured to control operation conditions of the non-volatile memory device and is arranged on a second surface of the second substrate, the second surface of the second substrate being opposite to the first surface of the second substrate of the second chip.

公开(公告)号：US20230060469A1

公开(公告)日：2023-03-02

申请号：US17854287

申请日：2022-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Chu OH ,  Junyeong SEOK ,  Younggul SONG ,  Byungchul JANG ,  Joonsung LIM

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  G06F11/10

Abstract: A three-dimensional (3D) storage device using wafer-to-wafer bonding is disclosed. In the storage device, a first chip including a peripheral circuit region including a first control logic circuit configured to control operation modes of a nonvolatile memory (NVM) device is wafer-bonded with a second chip including 3D arrays of NVM cells, and a memory controller includes a third chip including a control circuit region. The control circuit region of the third chip includes a second control logic circuit associated with operation conditions of the NVM device, and the second control logic circuit includes a serializer/deserializer (SERDES) interface configured to share random access memory (RAM) in the memory controller and transmit and receive data to and from the NVM device.

公开(公告)号：US20230197158A1

公开(公告)日：2023-06-22

申请号：US17810777

申请日：2022-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Chu OH ,  Junyeong SEOK ,  Younggul SONG

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/0483

Abstract: A nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of word-lines, a plurality of memory cells provided in a plurality of channel holes and a word-line cut region extending in a first horizontal direction and dividing the word-lines into a plurality of memory blocks. A plurality of target memory cells coupled to each of the plurality of word-lines are grouped into outer cells and inner cells based on a location index of each of the plurality of memory cells. The control circuit controls a program operation on target memory cells coupled to a target word-line of the plurality of word-lines such that each of the outer cells stores a first number of bits and each of the inner cells stores a second number of bits. The second number is a natural number greater than the first number.

公开(公告)号：US20230189528A1

公开(公告)日：2023-06-15

申请号：US17896546

申请日：2022-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younggul SONG ,  Junyeong SEOK ,  Eunchu OH

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11573 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor device may include a plurality of gate electrode layers stacked in a first direction perpendicular to an upper surface of a substrate, a plurality of channel structures penetrating through the plurality of gate electrode layers and extending in the first direction, a plurality of first isolation structures extending in a second direction parallel to the upper surface of the substrate and dividing the plurality of gate electrode layers into a plurality of blocks, and a plurality of second isolation structures extending in the second direction within each of the plurality of blocks. Each of the plurality of first isolation structures may include only a first vertical insulating layer, and at least one of the plurality of second isolation structures may include a second vertical insulating layer and a conductive layer.

公开(公告)号：US20240311011A1

公开(公告)日：2024-09-19

申请号：US18674089

申请日：2024-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyeong SEOK ,  Younggul SONG ,  Eun Chu OH ,  Byungchul JANG ,  Joonsung LIM

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/064 ,  G06F3/0679

Abstract: In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.

公开(公告)号：US20230207017A1

公开(公告)日：2023-06-29

申请号：US17810894

申请日：2022-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Eun Chu OH ,  Junyeong SEOK ,  Younggul SONG

IPC: G11C16/10 ,  G11C16/28 ,  G11C16/34 ,  G11C16/08 ,  G11C16/32

CPC classification number: G11C16/102 ,  G11C16/28 ,  G11C16/3495 ,  G11C16/08 ,  G11C16/32

Abstract: A storage device includes a nonvolatile memory device and a storage controller to control operation of the nonvolatile memory device. The storage controller assigns a program operation associated with data to be programmed, to one of a first program operation or a second program operation, controls the nonvolatile memory device to perform the first program operation on first memory blocks and to perform the second program operation on at least one second memory block, and controls the nonvolatile memory to select one of the first program operation on a third memory block in an erase state or the second program operation on the second memory block, and to perform the selected program operation after the first program operation on the first memory blocks is completed.

公开(公告)号：US20230153202A1

公开(公告)日：2023-05-18

申请号：US17965091

申请日：2022-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younggul SONG ,  Byungchul JANG ,  Junyeong SEOK ,  Eun Chu OH

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0793

Abstract: A method of operating a memory system that comprises a memory device including a plurality of memory blocks and a memory controller, includes detecting a first memory block having a degradation count greater than or equal to a first reference value by the memory controller. A first command for the first memory block is transmitted to the memory device by the memory controller. A first voltage is applied to all of a plurality of word lines connected to the first memory block and a second voltage to a bit line connected to the first memory block in response to the first command by the memory device. The first voltage is greater than a voltage applied to turn on memory cells connected to all of the plurality of word lines. The second voltage is greater than a voltage applied to the bit line during program, read or erase operations.