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    Multi-pulse programming cycle of non-volatile memory for enhanced de-trapping
    1.
    发明授权
    Multi-pulse programming cycle of non-volatile memory for enhanced de-trapping 有权
    多脉冲编程周期的非易失性存储器，用于增强去捕获

    公开(公告)号：US09218874B1

    公开(公告)日：2015-12-22

    申请号：US14456853

    申请日：2014-08-11

    Applicant: SanDisk Technologies Inc.

    Inventor： Yee Lih Koh ,  Tien-chien Kuo ,  Man Mui ,  Juan Lee

    IPC: G11C11/34 ,  G11C11/56 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10

    CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5648

    Abstract: When writing a multi-state non-volatile memory, a de-trapping operation is included in the programming cycle. To reduce the performance penalty of including a de-trapping operation, the programming cycle of a single series of increasing pulses alternating with verify operations is replaced with a cycle including a pulse from each of two or more staircases, where each staircase is for a corresponding subset of the data states. After the multiple pulses, but before the following verify, a de-trapping operation is inserted in the programming cycle.

    Abstract translation: 在写入多状态非易失性存储器时，编程周期中包含解除捕获操作。 为了降低包括解除捕获操作的性能损失，与验证操作交替的单个增加脉冲序列的编程周期被包括来自两个或多个楼梯中的每一个的脉冲的周期替换，其中每个阶梯用于相应的 数据状态的子集。 在多个脉冲之后，但在进行以下验证之前，在编程周期中插入解除捕获操作。

    Adaptive selective bit line pre-charge for current savings and fast programming
    2.
    发明授权
    Adaptive selective bit line pre-charge for current savings and fast programming 有权
    自适应选择性位线预充电用于当前节省和快速编程

    公开(公告)号：US09595345B2

    公开(公告)日：2017-03-14

    申请号：US14454702

    申请日：2014-08-07

    Applicant: SanDisk Technologies Inc.

    Inventor： Man L Mui ,  Yee Lih Koh ,  Yenlung Li ,  Cynthia Hsu

    IPC: G11C16/00 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56 ,  G11C16/24 ,  G11C16/04

    CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C2211/5621

    Abstract: Techniques are provided for efficiently performing programming operations in a memory device. In particular, power consumption is reduced in sensing circuitry by avoiding pre-charging of bit lines for certain memory cells at certain times during a programming operation. One approach uses knowledge of the different phases of a programming operation to reduce the number of unnecessary bit line pre-charges. For example, during the lower program loop numbers of a programming operation, bit line pre-charging may occur for lower data states but not for higher data states. Similarly, during the higher program loop numbers, bit line pre-charging may occur for higher data states but not for lower data states. In another approach, which may or may not incorporate knowledge of the different phases of a programming operation, the setting of the bit line pre-charge can be updated at least once after it is initially set in the verify portion.

    Abstract translation: 提供了用于在存储器件中有效执行编程操作的技术。 特别地，通过在编程操作期间的特定时间避免某些存储器单元的位线的预充电，感测电路中的功耗降低。 一种方法使用编程操作的不同阶段的知识来减少不必要的位线预充电的数量。 例如，在编程操作的较低编程环路编号期间，对于较低的数据状态而言可能会发生位线预充电，但对于较高的数据状态而言可能会发生位线预充电。 类似地，在较高的程序循环数期间，对于较高的数据状态而言，位线预充电可能发生，但是对于较低的数据状态则不会发生位线预充电。 在另一种可能或可能不包含编程操作的不同阶段的知识的方法中，位线预充电的设置可以在最初设置在验证部分中之后至少更新一次。

    NON-VOLATILE STORAGE WITH JOINT HARD BIT AND SOFT BIT READING
    3.
    发明申请
    NON-VOLATILE STORAGE WITH JOINT HARD BIT AND SOFT BIT READING 审中-公开
    非易失性存储，具有接合硬点和软位读取

    公开(公告)号：US20140071761A1

    公开(公告)日：2014-03-13

    申请号：US13743502

    申请日：2013-01-17

    Applicant: SANDISK TECHNOLOGIES INC.

    Inventor： Eran Sharon ,  Idan Alrod ,  Yan Li ,  Yee Lih Koh ,  Tien-Chien Kuo

    IPC: G11C16/26

    CPC classification number: G11C16/26 ,  G06F11/1012 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C2211/5624 ,  G11C2211/5631 ,  G11C2211/5632

    Abstract: A system is disclosed for reading hard bit information and soft bit information from non-volatile storage. Some of the hard bit information and/or soft bit information is read concurrently by using different bit line voltages, different integration times, different sense levels within the sense amplifiers, or other techniques. A method is disclosed for determining the hard bits and soft bits in real time based on sensed hard bit information and soft bit information.

    Abstract translation: 公开了用于从非易失性存储器读取硬比特信息和软比特信息的系统。 一些硬比特信息和/或软比特信息通过使用不同的位线电压，不同的积分时间，读出放大器内的不同感测电平或其他技术同时读出。 公开了一种基于感测的硬比特信息和软比特信息来实时确定硬比特和软比特的方法。

    Adaptive Selective Bit Line Pre-Charge For Current Savings And Fast Programming
    4.
    发明申请
    Adaptive Selective Bit Line Pre-Charge For Current Savings And Fast Programming 有权
    自适应选择性位线预充电用于节省电流和快速编程

    公开(公告)号：US20160042802A1

    公开(公告)日：2016-02-11

    申请号：US14454702

    申请日：2014-08-07

    Applicant: SanDisk Technologies Inc.

    Inventor： Man L. Mui ,  Yee Lih Koh ,  Yenlung Li ,  Cynthia Hsu

    IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10

    CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C2211/5621

    Abstract: Techniques are provided for efficiently performing programming operations in a memory device. In particular, power consumption is reduced in sensing circuitry by avoiding pre-charging of bit lines for certain memory cells at certain times during a programming operation. One approach uses knowledge of the different phases of a programming operation to reduce the number of unnecessary bit line pre-charges. For example, during the lower program loop numbers of a programming operation, bit line pre-charging may occur for lower data states but not for higher data states. Similarly, during the higher program loop numbers, bit line pre-charging may occur for higher data states but not for lower data states. In another approach, which may or may not incorporate knowledge of the different phases of a programming operation, the setting of the bit line pre-charge can be updated at least once after it is initially set in the verify portion.

    Abstract translation: 提供了用于在存储器件中有效执行编程操作的技术。 特别地，通过在编程操作期间的特定时间避免某些存储器单元的位线的预充电，感测电路中的功耗降低。 一种方法使用编程操作的不同阶段的知识来减少不必要的位线预充电的数量。 例如，在编程操作的较低编程环路编号期间，对于较低的数据状态而言可能会发生位线预充电，而对于较高的数据状态则不会发生位线预充电。 类似地，在较高的程序循环数期间，对于较高的数据状态而言，位线预充电可能发生，但是对于较低的数据状态则不会发生位线预充电。 在另一种可能或可能不包含编程操作的不同阶段的知识的方法中，位线预充电的设置可以在最初设置在验证部分中之后至少更新一次。

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