-
1.发明申请Adaptive Selective Bit Line Pre-Charge For Current Savings And Fast Programming 有权自适应选择性位线预充电用于节省电流和快速编程公开(公告)号：US20160042802A1
公开(公告)日：2016-02-11
申请号：US14454702
申请日：2014-08-07
发明人： Man L. Mui , Yee Lih Koh , Yenlung Li , Cynthia Hsu
CPC分类号： G11C16/3459 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/26 , G11C2211/5621
摘要： Techniques are provided for efficiently performing programming operations in a memory device. In particular, power consumption is reduced in sensing circuitry by avoiding pre-charging of bit lines for certain memory cells at certain times during a programming operation. One approach uses knowledge of the different phases of a programming operation to reduce the number of unnecessary bit line pre-charges. For example, during the lower program loop numbers of a programming operation, bit line pre-charging may occur for lower data states but not for higher data states. Similarly, during the higher program loop numbers, bit line pre-charging may occur for higher data states but not for lower data states. In another approach, which may or may not incorporate knowledge of the different phases of a programming operation, the setting of the bit line pre-charge can be updated at least once after it is initially set in the verify portion.
摘要翻译： 提供了用于在存储器件中有效执行编程操作的技术。 特别地，通过在编程操作期间的特定时间避免某些存储器单元的位线的预充电，感测电路中的功耗降低。 一种方法使用编程操作的不同阶段的知识来减少不必要的位线预充电的数量。 例如，在编程操作的较低编程环路编号期间，对于较低的数据状态而言可能会发生位线预充电，而对于较高的数据状态则不会发生位线预充电。 类似地，在较高的程序循环数期间，对于较高的数据状态而言，位线预充电可能发生，但是对于较低的数据状态则不会发生位线预充电。 在另一种可能或可能不包含编程操作的不同阶段的知识的方法中，位线预充电的设置可以在最初设置在验证部分中之后至少更新一次。
-
公开(公告)号：US20140269083A1
公开(公告)日：2014-09-18
申请号：US14290891
申请日：2014-05-29
发明人： Man L. Mui , Teruhiko Kamei , Yingda Dong , Ken Oowada , Yosuke Kato , Fumitoshi Ito , Seungpil Lee
IPC分类号： G11C16/28
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/26 , G11C2211/5621
摘要： Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.
-
公开(公告)号：US20150092496A1
公开(公告)日：2015-04-02
申请号：US14561841
申请日：2014-12-05
发明人： Deepanshu Dutta , Ken Oowada , Masaaki Higashitani , Man L. Mui
CPC分类号： G11C16/10 , G11C7/12 , G11C11/5628 , G11C16/12 , G11C16/24 , G11C16/3459
摘要： A program operation for a set of non-volatile storage elements. A count is maintained of a number of program pulses which are applied to an individual storage element in a slow programming mode, and an associated bit line voltage is adjusted based on the count. Different bit line voltages can be used, having a common step size or different steps sizes. As a result, the change in threshold voltage of the storage element within the slow programming mode, with each program pulse can be made uniform, resulting in improved programming accuracy. Latches maintain the count of program pulses experienced by the associated storage element, while in the slow programming mode. The storage element is in a fast programming mode when its threshold voltage is below a lower verify level, and in the slow programming mode when its threshold voltage is between the lower verify level and a higher verify level.
摘要翻译： 用于一组非易失性存储元件的程序操作。 维持以慢编程模式施加到单个存储元件的多个编程脉冲的计数，并且基于计数调整相关联的位线电压。 可以使用不同的位线电压，具有公共的步长或不同的步长。 结果，缓慢编程模式下的存储元件的阈值电压的变化可以使每个编程脉冲均匀，从而提高编程精度。 在缓慢编程模式下，锁存器保持相关存储元件所经历的程序脉冲计数。 当其阈值电压低于较低验证电平时，存储元件处于快速编程模式，而当其阈值电压处于较低验证电平和较高验证电平之间时，存储元件处于慢速编程模式。
-
4.发明授权Bit line current trip point modulation for reading nonvolatile storage elements 有权用于读取非易失性存储元件的位线电流跳变点调制公开(公告)号：US08942047B2
公开(公告)日：2015-01-27
申请号：US14290891
申请日：2014-05-29
发明人： Man L. Mui , Teruhiko Kamei , Yingda Dong , Ken Oowada , Yosuke Kato , Fumitoshi Ito , Seungpil Lee
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/26 , G11C2211/5621
摘要： Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.
摘要翻译： 在选择要被感测的非易失性存储元件时，系统获得关于这些非易失性存储元件的位置的信息，至少部分地基于该信息来确定感测参数，对电荷存储装置进行预充电，并且在保持 这些存储单元的位线的电压电平处于恒定值，将参考信号施加到这些非易失性存储元件一定的持续时间，然后确定在一定持续时间内由这些非易失性存储元件 非易失存储元件超过预定值。
-
公开(公告)号：US08908444B2
公开(公告)日：2014-12-09
申请号：US13960360
申请日：2013-08-06
发明人： Xiying Costa , Seung Yu , Roy E. Scheuerlein , Haibo Li , Man L. Mui
IPC分类号： G11C16/00 , G11C16/16 , G11C16/14 , G11C16/24 , G11C11/56 , G11C16/34 , H01L29/792 , H01L27/115
CPC分类号： G11C16/16 , G11C11/5635 , G11C16/14 , G11C16/24 , G11C16/3445 , H01L27/11551 , H01L27/11582 , H01L29/7926
摘要： An erase operation for a 3D stacked memory device adjusts a start time of an erase period and/or a duration of the erase period for each storage element based on a position of the storage element. A voltage is applied to one or both drive ends of a NAND string to pre-charge a channel to a level which is sufficient to create gate-induced drain leakage at the select gate transistors. With timing based on a storage element's distance from the driven end, the control gate voltage is lowered to encourage tunneling of holes into a charge trapping layer in the erase period. The lowered control gate voltage results in a channel-to-control gate voltage which is sufficiently high to encourage tunneling. The duration of the erase period is also increased when the distance from the driven end is greater. As a result, a narrow erase distribution can be achieved.
-
6.发明申请SOFT ERASE OPERATION FOR 3D NON-VOLATILE MEMORY WITH SELECTIVE INHIBITING OF PASSED BITS 有权具有选择性抑制通过位置的3D非易失性存储器的软擦除操作公开(公告)号：US20140269081A1
公开(公告)日：2014-09-18
申请号：US14290224
申请日：2014-05-29
发明人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L. Mui
CPC分类号： G11C16/3445 , G11C5/02 , G11C11/5635 , G11C16/0483 , G11C16/14 , G11C16/16 , G11C16/344 , G11C16/3472 , G11C29/52 , H01L27/11582 , H01L29/7926
摘要： An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits.
摘要翻译： 对于3D堆叠存储器件的擦除操作，当擦除操作进行时，选择性地抑制满足验证条件的存储器单元的子集。 结果，较快擦除的存储器单元不太可能被过度擦除并降低了降级。 可以根据子集的类型，通过控制选择栅极，漏极（SGD）晶体管线，位线或字线来独立地擦除存储器单元的每个子集。 对于SGD线子集或位线子集，SGD线或位线分别设置在抑制擦除的电平。 对于字线子集，字线电压浮动以禁止擦除。 可以为每个子集维持禁止或不禁止状态，并且每种类型的子集可以具有不同的最大允许数量的故障位。
-
公开(公告)号：US20140247662A1
公开(公告)日：2014-09-04
申请号：US14278374
申请日：2014-05-15
发明人： Yingda Dong , Cynthia Hsu , Man L. Mui , Manabu Sakai , Toru Miwa , Masaaki Higashitani
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C16/3468 , G11C16/349
摘要： In a programming operation of a 3D stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line layer, are programmed first as a test case to determine optimal conditions for programming the remaining memory cells on the selected word line layer. For example, a number of program-verify iterations or loops which are needed to program the initial set of memory cells an initial amount is determined. This loop count is then stored, e.g., within the initial set of memory cells, within the remaining memory cells, within memory cells on a remaining word line layer, or in a data register, and programming of the initial set of memory cells continues to completion. Subsequently, the loop count is retrieved and used to determine an optimal starting program voltage for programming the remaining memory cells.
-
8.发明申请3D Non-Volatile Memory With Control Gate Length Based On Memory Hole Diameter 审中-公开基于存储器孔径的控制栅极长度的3D非易失性存储器公开(公告)号：US20140362645A1
公开(公告)日：2014-12-11
申请号：US14279405
申请日：2014-05-16
发明人： Yingda Dong , Wendy Ou , Man L. Mui , Masaaki Higashitani
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/107 , G11C16/3418 , G11C16/3445 , G11C16/3472 , H01L27/11582 , H01L29/7926
摘要： A structure and fabrication process are provided for a 3D stacked non-volatile memory device which compensates for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, the word line layers are thicker at the bottom of the stack and can increase gradually from the bottom to the top of the stack. As a result, the length of the control gates of the memory cells is greater at the bottom of the stack. The capacitance between the control gate and a charge trapping layer increased in proportion to the length of the control gates. During programming, a narrower threshold voltage (Vth) distribution is achieved for these memory cells. The Vth distributions can be placed closer together and downshifted to allow lowering of a read pass voltage in a subsequent sensing operation, reducing read disturb.
摘要翻译： 提供了用于补偿存储器孔直径的变化的3D堆叠的非易失性存储器件的结构和制造工艺。 存储孔直径在堆叠底部较小，导致更严重的读取干扰。 为了补偿，字线层在堆叠的底部较厚，并且可以从堆叠的底部到顶部逐渐增加。 结果，存储器单元的控制栅极的长度在堆叠的底部更大。 控制栅极和电荷捕获层之间的电容与控制栅极的长度成比例地增加。 在编程期间，对于这些存储单元实现了较窄的阈值电压（Vth）分布。 可以将Vth分布放置得更靠近在一起并降档以允许在随后的感测操作中降低读通过电压，从而减少读取干扰。
-
9.发明申请Program And Read Operations For 3D Non-Volatile Memory Based On Memory Hole Diameter 有权基于记忆孔直径的3D非易失性存储器的编程和读取操作公开(公告)号：US20140362641A1
公开(公告)日：2014-12-11
申请号：US13910377
申请日：2013-06-05
发明人： Yingda Dong , Wendy Ou , Man L. Mui , Masaaki Higashitani
CPC分类号： G11C16/107 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3427 , H01L27/1157 , H01L27/11582
摘要： Techniques are provided for programming and reading memory cells in a 3D stacked non-volatile memory device by compensating for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, programming of memory cells at the lower word line layers is modified. In one approach, threshold voltage (Vth) distributions of one or more data states are narrowed during programming so that a lower read pass voltage can be used in a subsequent sensing operation. A sufficient spacing is maintained between the read pass voltage and the upper tail of the highest data state. The Vth distributions can be downshifted as well. In another approach, the read pass voltage is not lowered, but the lowest programmed state is upshifted to provide spacing from the upper tail of the erased state.
摘要翻译： 提供了通过补偿存储器孔直径的变化来编程和读取3D堆叠的非易失性存储器件中的存储器单元的技术。 存储孔直径在堆叠底部较小，导致更严重的读取干扰。 为了补偿，在较低字线层处的存储器单元的编程被修改。 在一种方法中，编程期间一个或多个数据状态的阈值电压（Vth）分布变窄，从而可以在随后的感测操作中使用较低的读通过电压。 在读通道电压和最高数据状态的上尾之间保持足够的间隔。 Vth分布也可以降档。 在另一种方法中，读通道电压不降低，但是最低编程状态被升高以提供与擦除状态的上尾的间隔。
-
10.发明授权Bit line current trip point modulation for reading nonvolatile storage elements 有权用于读取非易失性存储元件的位线电流跳变点调制公开(公告)号：US08885416B2
公开(公告)日：2014-11-11
申请号：US13754852
申请日：2013-01-30
发明人： Man L. Mui , Teruhiko Kamei , Yingda Dong , Ken Oowada , Yosuke Kato , Fumitoshi Ito , Seungpil Lee
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/26 , G11C2211/5621
摘要： Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.
摘要翻译： 在选择要被感测的非易失性存储元件时，系统获得关于这些非易失性存储元件的位置的信息，至少部分地基于该信息来确定感测参数，对电荷存储装置进行预充电，并且在保持 这些存储单元的位线的电压电平处于恒定值，将参考信号施加到这些非易失性存储元件一定的持续时间，然后确定在一定持续时间内由这些非易失性存储元件 非易失存储元件超过预定值。
-
-
-
-
-
-
-
-
-
搜索结果
24 条记录 (耗时 0.028 秒)
