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公开(公告)号：US09343156B1
公开(公告)日：2016-05-17
申请号：US14750250
申请日：2015-06-25
发明人： Man L Mui , Yongke Sun , Yingda Dong
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3459 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2211/5621
摘要： Programming techniques for a three-dimensional stacked memory device provide compensation for different intrinsic programming speeds of different groups of memory cells based on the groups' locations relative to the edge of a word line layer. A larger distance from the edge is associated with a faster programming speed. In one approach, the programming speeds are equalized by elevating a bit line voltage for the faster programming memory cells. Offset verify voltages which trigger a slow programming mode by elevating the bit line voltage can also be set based on the group locations. A programming speed can be measured during programming for a row or other group of cells to set the bit line voltage and/or the offset verify voltages. The compensation for the faster programming memory cells can also be based on their speed relative to the slower programming memory cells.
摘要翻译： 用于三维堆叠存储器件的编程技术基于相对于字线层的边缘的组的位置来为不同组的存储器单元的不同固有编程速度提供补偿。 距离边缘更大的距离与更快的编程速度相关联。 在一种方法中，通过提高用于更快编程存储器单元的位线电压来使编程速度相等。 也可以基于组位置来设置通过升高位线电压而触发缓慢编程模式的偏移验证电压。 可以在针对一行或另一组单元的编程期间测量编程速度，以设置位线电压和/或偏移验证电压。 更快编程存储单元的补偿也可以基于它们相对于较慢编程存储器单元的速度。
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2.发明授权Group word line erase and erase-verify methods for 3D non-volatile memory 有权用于3D非易失性存储器的组字线擦除和擦除验证方法公开(公告)号：US09330778B2
公开(公告)日：2016-05-03
申请号：US14524153
申请日：2014-10-27
发明人： Xiying Costa , Alex Mak , Johann Alsmeier , Man L Mui
CPC分类号： G11C16/3445 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/14 , G11C16/344 , H01L27/11582
摘要： An erase operation for a 3D stacked memory device assigns storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.
摘要翻译： 3D堆叠存储器件的擦除操作根据预期的擦除速度将存储元件分配给组。 然后根据它们的组擦除存储元件以提供更均匀的擦除深度和更严格的擦除分布。 在一种方法中，对于不同的组，控制栅极电压的设置不同，以减慢期望具有更快编程速度的存储元件。 可以将所有组一起设置为擦除或禁止状态。 在另一种方法中，控制栅极电压对于不同的组是公共的，但是对于每个组分别设置擦除或禁止状态。
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公开(公告)号：US08891308B1
公开(公告)日：2014-11-18
申请号：US14023920
申请日：2013-09-11
发明人： Wendy Ou , Man L Mui , Yingda Dong , Masaaki Higashitani
CPC分类号： G11C16/16 , G11C11/5635 , G11C16/0483 , G11C16/14
摘要： Techniques are provided for erasing memory cells in a 3D stacked non-volatile memory device in a way which avoids prolonging erase time as the erase speed deceases due to the accumulation of program-erase cycles. In particular, a step size for erase pulses can be set which is a function of the number of program-erase cycles, e.g., as indicated by a count of program-erase cycles, a loop count during programming which is a function of programming speed, or an initial program voltage which is a function of programming speed. Further, the erase operation can account for different erase speeds of memory cells in different word line layers.
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公开(公告)号：US09171632B2
公开(公告)日：2015-10-27
申请号：US14071288
申请日：2013-11-04
发明人： Yingda Dong , Man L Mui , Hitoshi Miwa
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/3427 , H01L27/1157 , H01L27/11582
摘要： A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates non-conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling.
摘要翻译： 用于3D堆叠存储器件的读取处理为未选择的存储器串提供最佳级别的通道升压，以抑制正常和弱擦除类型的读取干扰。 通过控制位线（Vbl），漏极侧选择栅极（Vsgd_unsel），源极选择栅极（Vsgs_unsel），存储器件的选定电平（字线层）（Vcg_sel）的电压，以及 未选择的内存设备级别（Vcg_unsel）。 通过初始使漏极侧和源极选择栅极不导通，可以提高通道，以允许来自增加的Vcg_unsel的电容耦合。 然后通过升高Vsgd_unsel和/或Vsgs_unsel来使漏极侧和/或源极侧选择栅极导通，从而中断升压。 另外，当Vcg_unsel仍然增加时，可以通过使漏极侧和/或源极侧选择栅极再次导通而发生升压。 或者，通道可以在Vbl驱动。 两级升压驱动Vbl上的通道，然后通过电容耦合提供升压。
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5.发明授权Program and read operations for 3D non-volatile memory based on memory hole diameter 有权基于存储器孔径对3D非易失性存储器进行编程和读取操作公开(公告)号：US08982626B2
公开(公告)日：2015-03-17
申请号：US13910377
申请日：2013-06-05
发明人： Yingda Dong , Wendy Ou , Man L Mui , Masaaki Higashitani
CPC分类号： G11C16/107 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3427 , H01L27/1157 , H01L27/11582
摘要： Techniques are provided for programming and reading memory cells in a 3D stacked non-volatile memory device by compensating for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, programming of memory cells at the lower word line layers is modified. In one approach, threshold voltage (Vth) distributions of one or more data states are narrowed during programming so that a lower read pass voltage can be used in a subsequent sensing operation. A sufficient spacing is maintained between the read pass voltage and the upper tail of the highest data state. The Vth distributions can be downshifted as well. In another approach, the read pass voltage is not lowered, but the lowest programmed state is upshifted to provide spacing from the upper tail of the erased state.
摘要翻译： 提供了通过补偿存储器孔直径的变化来编程和读取3D堆叠的非易失性存储器件中的存储器单元的技术。 存储孔直径在堆叠底部较小，导致更严重的读取干扰。 为了补偿，在较低字线层处的存储器单元的编程被修改。 在一种方法中，编程期间一个或多个数据状态的阈值电压（Vth）分布变窄，从而可以在随后的感测操作中使用较低的读通过电压。 在读通道电压和最高数据状态的上尾之间保持足够的间隔。 Vth分布也可以降档。 在另一种方法中，读通道电压不降低，但是最低编程状态被升高以提供与擦除状态的上尾的间隔。
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公开(公告)号：US08964480B2
公开(公告)日：2015-02-24
申请号：US13932384
申请日：2013-07-01
发明人： Man L Mui , Yingda Dong , Chris Avila
CPC分类号： G11C16/3459 , G11C11/5635 , G11C11/5642 , G11C13/004 , G11C16/26 , G11C16/344 , G11C16/3454
摘要： A number (Nwl) of programmed word lines in a block of NAND strings is determined by measuring a reference combined current (Iref) in the block when all of the memory cells are in a conductive state. Subsequently, to determine if a word line is a programmed word line, an additional combined current (Iadd) in the block is measured with a demarcation voltage applied to the selected word line. The selected word line is determined to be programmed word lines if Idd is less than Iref by at least a margin. Nwl can be used to adjust an erase-verify test of an erase operation by making the erase-verify test relatively hard to pass when the number is relatively small and relatively easy to pass when the number is relatively large. Or, Nwl can be used to identify a next word line to program in the block.
摘要翻译： 通过在所有存储单元处于导通状态时测量块中的参考组合电流（Iref）来确定NAND串块中的编程字线的数量（Nwl）。 随后，为了确定字线是否是编程字线，块中的附加组合电流（Iadd）是用施加到所选字线的分界电压来测量的。 如果Idd小于Iref至少有余量，则所选字线被确定为编程字线。 当数字相对较小时，通过使擦除验证测试相对难于通过，当数量相对较大时，Nwl可用于调整擦除操作的擦除验证测试。 或者，Nwl可用于标识块中的下一个字线进行编程。
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公开(公告)号：US20140247661A1
公开(公告)日：2014-09-04
申请号：US14279618
申请日：2014-05-16
发明人： Xiying Costa , Seung Yu , Roy E Scheuerlein , Haibo Li , Man L Mui
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C11/5635 , G11C16/14 , G11C16/24 , G11C16/3445 , H01L27/11551 , H01L27/11582 , H01L29/7926
摘要： An erase operation for a 3D stacked memory device adjusts a start time of an erase period and/or a duration of the erase period for each storage element based on a position of the storage element. A voltage is applied to one or both drive ends of a NAND string to pre-charge a channel to a level which is sufficient to create gate-induced drain leakage at the select gate transistors. With timing based on a storage element's distance from the driven end, the control gate voltage is lowered to encourage tunneling of holes into a charge trapping layer in the erase period. The lowered control gate voltage results in a channel-to-control gate voltage which is sufficiently high to encourage tunneling. The duration of the erase period is also increased when the distance from the driven end is greater. As a result, a narrow erase distribution can be achieved.
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公开(公告)号：US09142298B2
公开(公告)日：2015-09-22
申请号：US13940504
申请日：2013-07-12
发明人： Yingda Dong , Cynthia Hsu , Man L Mui , Manabu Sakai , Toru Miwa , Masaaki Higashitani
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C16/3468 , G11C16/349
摘要： In a programming operation of a 3D stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line layer, are programmed first as a test case to determine optimal conditions for programming the remaining memory cells on the selected word line layer. For example, a number of program-verify iterations or loops which are needed to program the initial set of memory cells an initial amount is determined. This loop count is then stored, e.g., within the initial set of memory cells, within the remaining memory cells, within memory cells on a remaining word line layer, or in a data register, and programming of the initial set of memory cells continues to completion. Subsequently, the loop count is retrieved and used to determine an optimal starting program voltage for programming the remaining memory cells.
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9.发明授权公开(公告)号：US08873293B1
公开(公告)日：2014-10-28
申请号：US14279611
申请日：2014-05-16
发明人： Wendy Ou , Man L Mui , Yingda Dong , Masaaki Higashitani
CPC分类号： G11C16/16 , G11C11/5635 , G11C16/0483 , G11C16/14
摘要： Techniques are provided for erasing memory cells in a 3D stacked non-volatile memory device in a way which avoids prolonging erase time as the erase speed deceases due to the accumulation of program-erase cycles. In particular, a step size for erase pulses can be set which is a function of the number of program-erase cycles, e.g., as indicated by a count of program-erase cycles, a loop count during programming which is a function of programming speed, or an initial program voltage which is a function of programming speed. Further, the erase operation can account for different erase speeds of memory cells in different word line layers.
摘要翻译： 提供了以3D堆叠的非易失性存储器件中的存储器单元擦除的技术，避免了擦除速度由于编程擦除周期的累积而消失，从而延长了擦除时间。 特别地，可以设置擦除脉冲的步长，其是编程擦除周期的数量的函数，例如，如编程擦除周期的计数所示，编程期间的循环计数是编程速度的函数 或作为编程速度的函数的初始编程电压。 此外，擦除操作可以解释不同字线层中存储单元的不同擦除速度。
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公开(公告)号：US08830755B1
公开(公告)日：2014-09-09
申请号：US14277311
申请日：2014-05-14
发明人： Yingda Dong , Man L Mui , Hitoshi Miwa
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/3427 , H01L27/1157 , H01L27/11582
摘要： A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates non-conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling.
摘要翻译： 用于3D堆叠存储器件的读取处理为未选择的存储器串提供最佳级别的通道升压，以抑制正常和弱擦除类型的读取干扰。 通过控制位线（Vbl），漏极侧选择栅极（Vsgd_unsel），源极选择栅极（Vsgs_unsel），存储器件的选定电平（字线层）（Vcg_sel）的电压，以及 未选择的内存设备级别（Vcg_unsel）。 通过初始使漏极侧和源极选择栅极不导通，可以提高通道，以允许来自增加的Vcg_unsel的电容耦合。 然后通过升高Vsgd_unsel和/或Vsgs_unsel来使漏极侧和/或源极侧选择栅极导通，从而中断升压。 另外，当Vcg_unsel仍然增加时，可以通过使漏极侧和/或源极侧选择栅极再次导通而发生升压。 或者，通道可以在Vbl驱动。 两级升压驱动Vbl上的通道，然后通过电容耦合提供升压。
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