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公开(公告)号：US20170256320A1
公开(公告)日：2017-09-07
申请号：US15062661
申请日：2016-03-07
发明人： Murong Lang , Deepanshu Dutta , Cynthia Hsu
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/3445 , G11C16/3459
摘要： Techniques are provided for optimizing the programming of memory cells by obtaining a metric which indicates a program or erase rate of the memory cells. In one approach, a count of pulses used to program the cells to different verify levels of respective data states is stored. A slope of a straight line fit of data points is then obtained. Each data point can include one of the verify levels and a corresponding one of the counts. An optimal step size is determined based on the slope. The counts may exclude one or more initial program voltages while the cells are programmed sufficiently to allow faster and slower cells to be distinguished, e.g., in a natural threshold voltage distribution. An erase depth can also be adjusted. The cells can be programmed in a separate evaluation or during programming of user data.
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公开(公告)号：US09201788B1
公开(公告)日：2015-12-01
申请号：US14520909
申请日：2014-10-22
发明人： Chris Avila , Gautam Dusija , Deepak Raghu , Cynthia Hsu , Changyuan Chen , Farookh Moogat
CPC分类号： G06F12/0246 , G06F3/061 , G06F3/0619 , G06F3/0629 , G06F3/064 , G06F3/0679 , G06F12/0638 , G06F2212/1024 , G06F2212/214 , G06F2212/7202 , G06F2212/7205 , G11C11/005 , G11C2211/5641
摘要： In a nonvolatile memory, hybrid blocks are initially written with only lower page data. The hybrid blocks later have middle and upper page data written. For high speed writes, data is written to a hybrid block and two or more Single Level Cell (SLC) blocks. The data from the SLC blocks are copied to the hybrid block at a later time in a folding operation.
摘要翻译： 在非易失性存储器中，混合块最初只写入较低页数据。 混合块后面有中上页数据写入。 对于高速写入，将数据写入混合块和两个或更多个单级单元（SLC）块。 来自SLC块的数据在稍后的折叠操作中被复制到混合块。
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公开(公告)号：US20150221391A1
公开(公告)日：2015-08-06
申请号：US14616309
申请日：2015-02-06
发明人： Tai-Yuan Tseng , Cynthia Hsu , Kwang Ho Kim
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/24 , G11C16/26 , G11C16/3459
摘要： A sense amplifier provides a state-dependent lockout to limit sensing to those bit lines that target a currently selected state for sensing. A sense amplifier scans program data prior to sensing at the verify levels corresponding to a plurality of states. When program data matches a currently selected state, the sense amplifier senses the bit line voltage during verification and writes the result to a data latch. The sense amplifier may write the result to a data latch for storing quick pass write data, in response to sensing at a low verify level for the selected state for example. When program data does not match the currently selected state, the sense amplifier skips sensing for the bit line. The sense amplifier locks out the bit line prior to sensing based on the program data.
摘要翻译： 读出放大器提供状态相关的锁定，以将感测限制到目标为当前选择的状态用于感测的那些位线。 感测放大器在对应于多个状态的验证电平进行感测之前扫描程序数据。 当程序数据与当前选择的状态相匹配时，读出放大器在验证期间感测位线电压，并将结果写入数据锁存器。 响应于针对例如选定状态的低验证电平的感测，读出放大器可将结果写入用于存储快速写入数据的数据锁存器。 当程序数据与当前选择的状态不匹配时，读出放大器跳过位线的检测。 读出放大器根据程序数据在感测之前锁定位线。
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4.发明授权Adaptive selective bit line pre-charge for current savings and fast programming 有权自适应选择性位线预充电用于当前节省和快速编程公开(公告)号：US09595345B2
公开(公告)日：2017-03-14
申请号：US14454702
申请日：2014-08-07
发明人： Man L Mui , Yee Lih Koh , Yenlung Li , Cynthia Hsu
CPC分类号： G11C16/3459 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/26 , G11C2211/5621
摘要： Techniques are provided for efficiently performing programming operations in a memory device. In particular, power consumption is reduced in sensing circuitry by avoiding pre-charging of bit lines for certain memory cells at certain times during a programming operation. One approach uses knowledge of the different phases of a programming operation to reduce the number of unnecessary bit line pre-charges. For example, during the lower program loop numbers of a programming operation, bit line pre-charging may occur for lower data states but not for higher data states. Similarly, during the higher program loop numbers, bit line pre-charging may occur for higher data states but not for lower data states. In another approach, which may or may not incorporate knowledge of the different phases of a programming operation, the setting of the bit line pre-charge can be updated at least once after it is initially set in the verify portion.
摘要翻译： 提供了用于在存储器件中有效执行编程操作的技术。 特别地，通过在编程操作期间的特定时间避免某些存储器单元的位线的预充电，感测电路中的功耗降低。 一种方法使用编程操作的不同阶段的知识来减少不必要的位线预充电的数量。 例如，在编程操作的较低编程环路编号期间，对于较低的数据状态而言可能会发生位线预充电，但对于较高的数据状态而言可能会发生位线预充电。 类似地，在较高的程序循环数期间，对于较高的数据状态而言，位线预充电可能发生，但是对于较低的数据状态则不会发生位线预充电。 在另一种可能或可能不包含编程操作的不同阶段的知识的方法中，位线预充电的设置可以在最初设置在验证部分中之后至少更新一次。
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公开(公告)号：US20140247662A1
公开(公告)日：2014-09-04
申请号：US14278374
申请日：2014-05-15
发明人： Yingda Dong , Cynthia Hsu , Man L. Mui , Manabu Sakai , Toru Miwa , Masaaki Higashitani
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C16/3468 , G11C16/349
摘要： In a programming operation of a 3D stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line layer, are programmed first as a test case to determine optimal conditions for programming the remaining memory cells on the selected word line layer. For example, a number of program-verify iterations or loops which are needed to program the initial set of memory cells an initial amount is determined. This loop count is then stored, e.g., within the initial set of memory cells, within the remaining memory cells, within memory cells on a remaining word line layer, or in a data register, and programming of the initial set of memory cells continues to completion. Subsequently, the loop count is retrieved and used to determine an optimal starting program voltage for programming the remaining memory cells.
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6.发明授权公开(公告)号：US10013345B2
公开(公告)日：2018-07-03
申请号：US14489179
申请日：2014-09-17
发明人： Eran Erez , Cynthia Hsu
CPC分类号： G06F12/0246 , G06F1/3275 , G06F3/0625 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G06F2212/7201 , G11C16/04 , G11C16/30 , Y02D10/14 , Y02D10/154
摘要： A storage module and method for scheduling memory operations for peak-power management and balancing are provided. In one embodiment, a storage module maintains a count of time slots over a period of time. The period of time corresponds to an amount of time between periodic power peaks of a memory operation. For each time slot, the storage module determines whether to commence a memory operation on one or more of the plurality of memory dies based on whether a power peak generated in the time slot by the memory operation would exceed a power threshold allowed for the time slot. Other embodiments are provided.
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公开(公告)号：US09552885B2
公开(公告)日：2017-01-24
申请号：US14794242
申请日：2015-07-08
发明人： Pitamber Shukla , Henry Chin , Dana Lee , Cynthia Hsu
CPC分类号： G11C16/16 , G11C11/5628 , G11C16/0483 , G11C16/26 , G11C16/3431 , G11C16/3445 , G11C2211/5644
摘要： A non-volatile memory system mitigates the effects of open block reading by analyzing the un-programmed region of a block before programming to determine a potential for read disturbance. The system may determine a read count value associated with open block reading of the memory block and/or perform partial block erase verification. To mitigate the effects of open block read disturbance, the system performs partial block erase for the un-programmed region of the memory block and/or limits programming in the un-programmed region.
摘要翻译： 非易失性存储器系统通过在编程之前分析块的未编程区域来确定读取干扰的可能性来缓解开放块读取的影响。 系统可以确定与存储块的开放块读取相关联的读取计数值和/或执行部分块擦除验证。 为了减轻开放块读取干扰的影响，系统对存储器块的未编程区域执行部分块擦除和/或限制非编程区域中的编程。
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公开(公告)号：US09552882B2
公开(公告)日：2017-01-24
申请号：US14616289
申请日：2015-02-06
发明人： Tai-Yuan Tseng , Yenlung Li , Cynthia Hsu , Kwang Ho Kim , Man L Mui
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/24 , G11C16/26 , G11C16/3459
摘要： A non-volatile memory includes an data latch structure for programming bit lines using at least three programming levels. A sense amplifier includes a first data latch for controlling the voltage of a corresponding bit line, and a second static data latch with scan circuitry for performing logic operations on the program data and sense results. The sense amplifier scans low verify sense results with program data to generate reduced programming data. The reduced programming data is transferred out of the first data latch after sensing for all states and the program data is scanned to generate program enable/inhibit data which is stored in the first data latch. After setting the bit line to a program inhibit or program enable level, the reduced programming data is transferred back to the first data latch. The bit lines for reduced programming are then adjusted to the reduced programming level.
摘要翻译： 非易失性存储器包括用于使用至少三个编程电平对位线进行编程的数据锁存结构。 读出放大器包括用于控制相应位线的电压的第一数据锁存器和具有扫描电路的第二静态数据锁存器，用于对程序数据执行逻辑运算并感测结果。 读出放大器利用程序数据扫描低校验感应结果，以产生简化的编程数据。 在对所有状态进行感测之后，减少的编程数据被传送出第一数据锁存器，并且扫描程序数据以产生存储在第一数据锁存器中的程序使能/禁止数据。 在将位线设置为程序禁止或程序使能电平之后，减小的编程数据被传送回第一数据锁存器。 然后，用于减少编程的位线被调整到降低的编程电平。
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公开(公告)号：US09324418B2
公开(公告)日：2016-04-26
申请号：US13925621
申请日：2013-06-24
发明人： Yingda Dong , Ken Oowada , Cynthia Hsu
CPC分类号： G11C11/5628 , G11C16/04 , G11C16/10 , G11C16/3468
摘要： A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V1, . . . , VN). Initially in the programming pass, the memory cells are verified relative to a test reference threshold value. This test reference threshold has a value offset past a designate demarcation threshold value Vi among the set by a predetermined margin. The overshoot of each memory cell when programmed past Vi, to be more or less than the margin can be determined. Accordingly, memory cells found to have an overshoot more than the margin are counteracted by having their programming rate slowed down in a subsequent portion of the programming pass so as to maintain a tighter threshold distribution.
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公开(公告)号：US20150331626A1
公开(公告)日：2015-11-19
申请号：US14520909
申请日：2014-10-22
发明人： Chris Avila , Gautam Dusija , Deepak Raghu , Cynthia Hsu , Changyuan Chen , Farookh Moogat
IPC分类号： G06F3/06
CPC分类号： G06F12/0246 , G06F3/061 , G06F3/0619 , G06F3/0629 , G06F3/064 , G06F3/0679 , G06F12/0638 , G06F2212/1024 , G06F2212/214 , G06F2212/7202 , G06F2212/7205 , G11C11/005 , G11C2211/5641
摘要： In a nonvolatile memory, hybrid blocks are initially written with only lower page data. The hybrid blocks later have middle and upper page data written. For high speed writes, data is written to a hybrid block and two or more Single Level Cell (SLC) blocks. The data from the SLC blocks are copied to the hybrid block at a later time in a folding operation.
摘要翻译： 在非易失性存储器中，混合块最初只写入较低页数据。 混合块后面有中上页数据写入。 对于高速写入，将数据写入混合块和两个或更多个单级单元（SLC）块。 来自SLC块的数据在稍后的折叠操作中被复制到混合块。
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