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公开(公告)号：US08909493B2
公开(公告)日：2014-12-09
申请号：US14279037
申请日：2014-05-15
发明人： Chris Avila , Yingda Dong , Man Lung Mui
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/10 , G11C16/26 , H01L27/115
摘要： A non-volatile memory system that has two or more sub-blocks in a block performs a check before accessing memory cells to see if the condition of a sub-block that is not being accessed could affect the memory cells being accessed. If such a sub-block is found then parameters used to access the cells may be modified according to a predetermined scheme.
摘要翻译： 在块内具有两个或多个子块的非易失性存储器系统在访问存储器单元之前执行检查，以查看未被访问的子块的状况是否可能影响被访问的存储器单元。 如果发现这样的子块，则可以根据预定方案修改用于访问小区的参数。
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公开(公告)号：US20140247660A1
公开(公告)日：2014-09-04
申请号：US14279037
申请日：2014-05-15
发明人： Chris Avila , Yingda Dong , Man Lung Mui
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/10 , G11C16/26 , H01L27/115
摘要： A non-volatile memory system that has two or more sub-blocks in a block performs a check before accessing memory cells to see if the condition of a sub-block that is not being accessed could affect the memory cells being accessed. If such a sub-block is found then parameters used to access the cells may be modified according to a predetermined scheme.
摘要翻译： 在块内具有两个或多个子块的非易失性存储器系统在访问存储器单元之前执行检查，以查看未被访问的子块的状况是否可能影响被访问的存储器单元。 如果发现这样的子块，则可以根据预定方案修改用于访问小区的参数。
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公开(公告)号：US20140226402A1
公开(公告)日：2014-08-14
申请号：US13765349
申请日：2013-02-12
发明人： Yacov Duzly , Alon Marcu , Yuval Kenan , Yan Li , Man Lung Mui , Seungpil Lee
IPC分类号： G11C16/10
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10
摘要： In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.
摘要翻译： 在闪速存储器中，通过在多页读取期间保持全局字线电压，并且通过同时将旧的所选字线从识别电压转换到读取电压并转换新的选择字，快速连续读取平面中的两页或多页 从读取电压到鉴别电压。
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4.发明申请TEMPERATURE BASED COMPENSATION DURING VERIFY OPERATIONS FOR NON-VOLATILE STORAGE 有权在非易失性存储的验证操作期间基于温度的补偿公开(公告)号：US20140036601A1
公开(公告)日：2014-02-06
申请号：US14048015
申请日：2013-10-07
发明人： Ken Oowada , Yingda Dong , Gerrit Jan Hemink , Man Lung Mui , Hao Nguyen , Seungpil Lee , Jong Park , Fanglin Zhang
IPC分类号： G11C16/34
CPC分类号： G11C16/06 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.
摘要翻译： 执行编程和读取过程的非易失性存储系统。 编程过程包括粗/精编程和验证操作。 通过测试两个不同的阈值电压电平来验证编程，同时通过测试存储器单元的电流水平并基于当前温度调整测试的电流水平，将相同的电压电平施加到存储器单元的控制栅极，使得 两个有效的测试阈值电压水平在温度变化上保持恒定。
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公开(公告)号：US08995195B2
公开(公告)日：2015-03-31
申请号：US13765349
申请日：2013-02-12
发明人： Yacov Duzly , Alon Marcu , Yuval Kenan , Yan Li , Man Lung Mui , Seungpil Lee
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10
摘要： In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.
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公开(公告)号：US08988941B2
公开(公告)日：2015-03-24
申请号：US13801800
申请日：2013-03-13
发明人： Chris Nga Yee Avila , Yingda Dong , Man Lung Mui
CPC分类号： G11C16/107 , G11C11/5635 , G11C16/24 , G11C16/3404 , G11C29/02 , G11C29/024 , G11C29/028 , G11C2029/0409
摘要： In a nonvolatile memory array in which a select transistor includes a charge storage element, the threshold voltage of the select transistor is monitored, and if the threshold voltage deviates from a desired threshold voltage range, charge is added to, or removed from the charge storage element to return the threshold voltage to the desired threshold voltage range.
摘要翻译： 在其中选择晶体管包括电荷存储元件的非易失性存储器阵列中，监视选择晶体管的阈值电压，并且如果阈值电压偏离期望的阈值电压范围，则将电荷添加到电荷存储器 元件将阈值电压返回到期望的阈值电压范围。
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公开(公告)号：US08908432B2
公开(公告)日：2014-12-09
申请号：US13755905
申请日：2013-01-31
发明人： Teruhiko Kamei , Seungpil Lee , Siu Lung Chan , Kwang Ho Kim , Man Lung Mui
CPC分类号： G11C16/28
摘要： Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria such as a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a memory plane. Within each zone, different bit line read voltages may be applied to different bit line groupings in order to compensate for systematic variations in bit line resistance between neighboring bit lines due to the use of multiple patterning lithography techniques such as spacer-based double patterning.
摘要翻译： 描述了用于补偿存储器单元感测期间位线电阻变化的方法。 位线电阻的变化可能会在同一芯片上面对芯片或平面到平面。 在一些实施例中，对于管芯上的每个管芯或存储器平面，可以基于诸如故障位数的感测标准来确定与多个区域相关联的多个位线读取电压。 多个区域中的每个区域可以与存储器平面内的存储器阵列区域相关联。 在每个区域内，可以将不同的位线读取电压施加到不同的位线分组，以便补偿相邻位线之间的位线电阻的系统变化，这是由于使用诸如基于间隔物的双重图案化的多重图案化光刻技术。
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公开(公告)号：US20140169095A1
公开(公告)日：2014-06-19
申请号：US13801800
申请日：2013-03-13
发明人： Chris Nga Yee Avila , Yingda Dong , Man Lung Mui
IPC分类号： G11C16/34
CPC分类号： G11C16/107 , G11C11/5635 , G11C16/24 , G11C16/3404 , G11C29/02 , G11C29/024 , G11C29/028 , G11C2029/0409
摘要： In a nonvolatile memory array in which a select transistor includes a charge storage element, the threshold voltage of the select transistor is monitored, and if the threshold voltage deviates from a desired threshold voltage range, charge is added to, or removed from the charge storage element to return the threshold voltage to the desired threshold voltage range.
摘要翻译： 在其中选择晶体管包括电荷存储元件的非易失性存储器阵列中，监视选择晶体管的阈值电压，并且如果阈值电压偏离期望的阈值电压范围，则将电荷添加到电荷存储器 元件将阈值电压返回到期望的阈值电压范围。
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公开(公告)号：US20140133232A1
公开(公告)日：2014-05-15
申请号：US13791286
申请日：2013-03-08
发明人： Chris Nga Yee Avila , Yingda Dong , Man Lung Mui
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/10 , G11C16/26 , H01L27/115
摘要： A non-volatile memory system that has two or more sub-blocks in a block performs a check before accessing memory cells to see if the condition of a sub-block that is not being accessed could affect the memory cells being accessed. If such a sub-block is found then parameters used to access the cells may be modified according to a predetermined scheme.
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10.发明申请NON-VOLATILE MEMORY AND METHOD WITH ADJUSTED TIMING FOR INDIVIDUAL PROGRAMMING PULSES 有权非易失性存储器和方法，用于个性化编程脉冲调整时序公开(公告)号：US20160099059A1
公开(公告)日：2016-04-07
申请号：US14508352
申请日：2014-10-07
发明人： Han Chen , Man Lung Mui , Kou Tei
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/32 , G11C2211/5622 , G11C2216/14
摘要： A non-volatile memory and method have programming circuitry that outputs a series of programming pulses of increasing voltage level to program in parallel a group of memory cells associated with a selected word line. Individual timing of the programming pulses such as rise and fall times of the pulse is optimally and dynamically adjusted according to the relative numbers of program-enabled and program-inhibited memory cells in the group associated with that pulse.
摘要翻译： 非易失性存储器和方法具有编程电路，其输出一系列具有增加的电压电平的编程脉冲以并行编程与所选字线相关联的一组存储器单元。 编程脉冲的单个定时（如脉冲的上升和下降时间）根据与脉冲相关联的组中的编程使能和程序禁止的存储器单元的相对数量被最佳和动态地调整。
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