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    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
    3.
    发明申请
    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
    薄膜晶体管阵列及其制造方法

    公开(公告)号：US20120138920A1

    公开(公告)日：2012-06-07

    申请号：US13099108

    申请日：2011-05-02

    申请人： Yoon Ho KHANG ,  Se Hwan YU ,  Chong Sup CHANG ,  Sang Ho PARK ,  Su-Hyoung KANG

    发明人： Yoon Ho KHANG ,  Se Hwan YU ,  Chong Sup CHANG ,  Sang Ho PARK ,  Su-Hyoung KANG

    IPC分类号： H01L29/12 ,  H01L21/336

    CPC分类号： H01L27/1225 ,  H01L29/7869

    摘要： A thin film transistor array panel is provided that includes: a gate electrode that is disposed on an insulating substrate; a gate insulating layer that is disposed on the gate electrode; an oxide semiconductor that is disposed on the gate insulating layer; a blocking layer that is disposed on the oxide semiconductor; a source electrode and a drain electrode that are disposed on the blocking layer; a passivation layer that is disposed on the source electrode and drain electrode; and a pixel electrode that is disposed on the passivation layer. The blocking layer includes a first portion that is covered by the source electrode and drain electrode and a second portion that is not covered by the source electrode and drain electrode, and the first portion and the second portion include different materials.

    摘要翻译： 提供薄膜晶体管阵列面板，其包括：设置在绝缘基板上的栅电极; 栅极绝缘层，设置在栅电极上; 设置在所述栅极绝缘层上的氧化物半导体; 设置在所述氧化物半导体上的阻挡层; 设置在所述阻挡层上的源电极和漏电极; 钝化层，其设置在所述源电极和所述漏电极上; 以及设置在钝化层上的像素电极。 阻挡层包括由源电极和漏电极覆盖的第一部分和未被源电极和漏电极覆盖的第二部分，并且第一部分和第二部分包括不同的材料。

    THIN FILM TRANSISTOR AND THIN FILM TRANSISTOR ARRAY PANEL
    5.
    发明申请
    THIN FILM TRANSISTOR AND THIN FILM TRANSISTOR ARRAY PANEL 有权
    薄膜晶体管和薄膜晶体管阵列

    公开(公告)号：US20130032794A1

    公开(公告)日：2013-02-07

    申请号：US13367076

    申请日：2012-02-06

    申请人： Yong Su LEE ,  Yoon Ho KHANG ,  Se Hwan YU ,  Chong Sup CHANG

    发明人： Yong Su LEE ,  Yoon Ho KHANG ,  Se Hwan YU ,  Chong Sup CHANG

    IPC分类号： H01L29/786 ,  B82Y99/00

    CPC分类号： H01L29/458 ,  H01L29/45 ,  H01L29/78618 ,  H01L29/7869

    摘要： Provided is a thin film transistor and thin film transistor panel array. The thin film transistor includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate and partially overlapping with the gate electrode; a source electrode and a drain electrode spaced apart from each other with respect to a channel region of the semiconductor layer; an insulating layer disposed between the gate electrode and the semiconductor layer; and a barrier layer disposed between the semiconductor layer and the source electrode and between the semiconductor layer and the drain electrode, in which the barrier layer comprises graphene. An ohmic contact is provided based on the type of material used for the semiconductor layer.

    摘要翻译： 提供了一种薄膜晶体管和薄膜晶体管阵列阵列。 薄膜晶体管包括：基板; 设置在所述基板上的栅电极; 设置在所述基板上并与所述栅电极部分重叠的半导体层; 源电极和漏电极相对于半导体层的沟道区彼此分开; 设置在所述栅电极和所述半导体层之间的绝缘层; 以及设置在所述半导体层和所述源电极之间以及所述半导体层和所述漏电极之间的阻挡层，其中所述阻挡层包括石墨烯。 基于用于半导体层的材料的类型提供欧姆接触。

    THIN FILM TRANSISTOR DISPLAY PANEL AND MANUFACTURING METHOD THEREOF
    6.
    发明申请
    THIN FILM TRANSISTOR DISPLAY PANEL AND MANUFACTURING METHOD THEREOF 有权
    薄膜晶体管显示面板及其制造方法

    公开(公告)号：US20120223300A1

    公开(公告)日：2012-09-06

    申请号：US13172200

    申请日：2011-06-29

    申请人： Su-Hyoung KANG ,  Yoon Ho KHANG ,  Dong Jo KIM ,  Hyun Jae NA

    发明人： Su-Hyoung KANG ,  Yoon Ho KHANG ,  Dong Jo KIM ,  Hyun Jae NA

    IPC分类号： H01L29/786 ,  H01L21/336

    CPC分类号： H01L27/1248 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/78606 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A thin film transistor array panel and a manufacturing method capable of forming an insulating layer made of different materials for a portion contacting an oxide semiconductor and a second portion without an additional process. The thin film transistor array panel includes: a gate electrode; a source electrode and a drain electrode spaced apart from each other, each of the source and drain electrodes comprising a lower layer and an upper layer; an insulating layer disposed between the gate electrode and the source and drain electrodes; a semiconductor, the source electrode and the drain electrode being electrically connected to the semiconductor; a first passivation layer contacting the lower layer of the source and drain electrodes but not contacting the upper layer of the source and drain electrodes; and a second passivation layer disposed on the upper layer of the source and drain electrodes. The first passivation layer may be made of silicon oxide, and the second passivation may be made of silicon nitride.

    摘要翻译： 一种薄膜晶体管阵列面板和能够形成由不同材料制成的绝缘层的制造方法，用于与氧化物半导体和第二部分接触的部分，而不需要额外的工艺。 薄膜晶体管阵列面板包括：栅电极; 源电极和漏电极彼此间隔开，源极和漏极中的每一个包括下层和上层; 绝缘层，设置在所述栅极电极和所述源极和漏极之间; 半导体，源电极和漏极电连接到半导体; 第一钝化层接触源极和漏极的下层，但不接触源极和漏极的上层; 以及设置在源电极和漏电极的上层上的第二钝化层。 第一钝化层可以由氧化硅制成，并且第二钝化可以由氮化硅制成。