公开(公告)号：US08735239B2

公开(公告)日：2014-05-27

申请号：US13197133

申请日：2011-08-03

申请人： Sangjine Park ,  Young Suk Jung ,  Boun Yoon ,  Jeongman Han ,  Byung-Kwon Cho

发明人： Sangjine Park ,  Young Suk Jung ,  Boun Yoon ,  Jeongman Han ,  Byung-Kwon Cho

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L27/10 ,  H01L29/80

CPC分类号： H01L21/823814 ,  H01L21/02068 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： Provided is a method of fabricating a semiconductor device. Gate patterns are formed on a substrate including an NMOS transistor region and a PMOS transistor region. A spacer structure is formed on sidewalls of the gate patterns. The substrate in the PMOS transistor region is etched using the gate patterns and the spacer structure as etching masks, and thereby a recessed region is formed. A compressive stress pattern is formed in the recessed region, and a sidewall of the compressive stress pattern protrudes upwardly from an upper surface of the substrate. A mask oxide layer is formed on a sidewall of the spacer structure. The mask oxide layer is formed to cover a portion of the sidewall of the compressive stress pattern that protrudes upwardly from the upper surface of the substrate.

摘要翻译： 提供一种制造半导体器件的方法。 栅极图案形成在包括NMOS晶体管区域和PMOS晶体管区域的衬底上。 间隔结构形成在栅极图案的侧壁上。 使用栅极图案和间隔结构作为蚀刻掩模蚀刻PMOS晶体管区域中的衬底，从而形成凹陷区域。 在凹陷区域中形成压缩应力图案，压缩应力图案的侧壁从基板的上表面向上突出。 在间隔结构的侧壁上形成掩模氧化物层。 掩模氧化物层被形成为覆盖从衬底的上表面向上突出的压缩应力图案的侧壁的一部分。

公开(公告)号：US20120094459A1

公开(公告)日：2012-04-19

申请号：US13197133

申请日：2011-08-03

申请人： Sanjine Park ,  Young Suk Jung ,  Boun Yoon ,  Jeongman Han ,  Byung-Kwon Cho

发明人： Sanjine Park ,  Young Suk Jung ,  Boun Yoon ,  Jeongman Han ,  Byung-Kwon Cho

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L21/823814 ,  H01L21/02068 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： Provided is a method of fabricating a semiconductor device. Gate patterns are formed on a substrate including an NMOS transistor region and a PMOS transistor region. A spacer structure is formed on sidewalls of the gate patterns. The substrate in the PMOS transistor region is etched using the gate patterns and the spacer structure as etching masks, and thereby a recessed region is formed. A compressive stress pattern is formed in the recessed region, and a sidewall of the compressive stress pattern protrudes upwardly from an upper surface of the substrate. A mask oxide layer is formed on a sidewall of the spacer structure. The mask oxide layer is formed to cover a portion of the sidewall of the compressive stress pattern that protrudes upwardly from the upper surface of the substrate.

摘要翻译： 提供一种制造半导体器件的方法。 栅极图案形成在包括NMOS晶体管区域和PMOS晶体管区域的衬底上。 间隔结构形成在栅极图案的侧壁上。 使用栅极图案和间隔结构作为蚀刻掩模蚀刻PMOS晶体管区域中的衬底，从而形成凹陷区域。 在凹陷区域中形成压缩应力图案，压缩应力图案的侧壁从基板的上表面向上突出。 在间隔结构的侧壁上形成掩模氧化物层。 掩模氧化物层被形成为覆盖从衬底的上表面向上突出的压缩应力图案的侧壁的一部分。

公开(公告)号：US08946026B2

公开(公告)日：2015-02-03

申请号：US13238284

申请日：2011-09-21

申请人： Sukhun Choi ,  Boun Yoon ,  Jae-Jik Baek ,  Byung-Kwon Cho

发明人： Sukhun Choi ,  Boun Yoon ,  Jae-Jik Baek ,  Byung-Kwon Cho

IPC分类号： H01L21/8238 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/32139 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

摘要： A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.

摘要翻译： 制造具有金属栅电极的半导体器件的方法包括在具有第一区域和第二区域的半导体衬底上形成绝缘层。 绝缘层形成为包括层间绝缘层和栅极绝缘层。 层间绝缘层具有分别设置在第一和第二区域中的第一和第二沟槽，并且栅极绝缘层至少覆盖第一和第二沟槽的至少底表面。 在具有绝缘层的基板上形成层叠金属层。 在层叠金属层上形成具有非光敏性的平坦化层。 使用干蚀刻工艺选择性地去除第一区域中的平坦化层，以暴露第一区域中的层压金属层，并形成覆盖第二区域中的层叠金属层的平坦化图案。

公开(公告)号：US20120129331A1

公开(公告)日：2012-05-24

申请号：US13238284

申请日：2011-09-21

申请人： Sukhun Choi ,  Boun Yoon ,  Jae-Jik Baek ,  Byung-Kwon Cho

发明人： Sukhun Choi ,  Boun Yoon ,  Jae-Jik Baek ,  Byung-Kwon Cho

IPC分类号： H01L21/28

CPC分类号： H01L21/32139 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

摘要： A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.

摘要翻译： 制造具有金属栅电极的半导体器件的方法包括在具有第一区域和第二区域的半导体衬底上形成绝缘层。 绝缘层形成为包括层间绝缘层和栅极绝缘层。 层间绝缘层具有分别设置在第一和第二区域中的第一和第二沟槽，并且栅极绝缘层至少覆盖第一和第二沟槽的至少底表面。 在具有绝缘层的基板上形成层叠金属层。 在层叠金属层上形成具有非光敏性的平坦化层。 使用干蚀刻工艺选择性地去除第一区域中的平坦化层，以暴露第一区域中的层压金属层，并形成覆盖第二区域中的层叠金属层的平坦化图案。

公开(公告)号：US20120049250A1

公开(公告)日：2012-03-01

申请号：US13191055

申请日：2011-07-26

申请人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Jae-Jik Baek ,  Byung-Kwon Cho

发明人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Jae-Jik Baek ,  Byung-Kwon Cho

IPC分类号： H01L29/78

CPC分类号： H01L29/7833 ,  H01L21/30608 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor integrated circuit device includes a substrate. A gate structure is formed on the substrate and includes a gate insulating film and a gate electrode. A first sidewall spacer is formed on two sidewalls of the gate structure. A second sidewall spacer is formed on the first sidewall spacer. A recess compensation film is interposed between the second sidewall spacer and the substrate. An epitaxial layer is in contact with the recess compensation film.

摘要翻译： 半导体集成电路器件包括衬底。 栅极结构形成在衬底上并且包括栅极绝缘膜和栅电极。 第一侧壁间隔件形成在栅极结构的两个侧壁上。 在第一侧壁间隔件上形成第二侧壁间隔物。 在第二侧壁间隔件和基板之间设置凹陷补偿膜。 外延层与凹部补偿膜接触。

公开(公告)号：US09443979B2

公开(公告)日：2016-09-13

申请号：US14455036

申请日：2014-08-08

申请人： Sang-Jine Park ,  Bo-Un Yoon ,  Ha-Young Jeon ,  Byung-Kwon Cho ,  Jeong-Nam Han

发明人： Sang-Jine Park ,  Bo-Un Yoon ,  Ha-Young Jeon ,  Byung-Kwon Cho ,  Jeong-Nam Han

IPC分类号： H01L29/78 ,  H01L27/08 ,  H01L21/28 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

CPC分类号： H01L29/66545 ,  H01L21/28114 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.

摘要翻译： 半导体器件包括限定沟槽的栅极间隔。 沟槽包括顺序地位于基板上的第一部分和第二部分。 第一部分的内表面具有锐角的斜面，并且第二部分的内表面具有相对于基底的直角或钝角的斜率。 栅电极填充沟槽的至少一部分。