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    Methods of fabricating a semiconductor device including metal gate electrodes
    3.
    发明授权
    Methods of fabricating a semiconductor device including metal gate electrodes 有权
    制造包括金属栅电极的半导体器件的方法

    公开(公告)号：US08946026B2

    公开(公告)日：2015-02-03

    申请号：US13238284

    申请日：2011-09-21

    申请人： Sukhun Choi ,  Boun Yoon ,  Jae-Jik Baek ,  Byung-Kwon Cho

    发明人： Sukhun Choi ,  Boun Yoon ,  Jae-Jik Baek ,  Byung-Kwon Cho

    IPC分类号： H01L21/8238 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L21/32139 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

    摘要： A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.

    摘要翻译： 制造具有金属栅电极的半导体器件的方法包括在具有第一区域和第二区域的半导体衬底上形成绝缘层。 绝缘层形成为包括层间绝缘层和栅极绝缘层。 层间绝缘层具有分别设置在第一和第二区域中的第一和第二沟槽，并且栅极绝缘层至少覆盖第一和第二沟槽的至少底表面。 在具有绝缘层的基板上形成层叠金属层。 在层叠金属层上形成具有非光敏性的平坦化层。 使用干蚀刻工艺选择性地去除第一区域中的平坦化层，以暴露第一区域中的层压金属层，并形成覆盖第二区域中的层叠金属层的平坦化图案。

    METHODS OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING METAL GATE ELECTRODES
    4.
    发明申请
    METHODS OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING METAL GATE ELECTRODES 有权
    制造包括金属栅极电极的半导体器件的方法

    公开(公告)号：US20120129331A1

    公开(公告)日：2012-05-24

    申请号：US13238284

    申请日：2011-09-21

    申请人： Sukhun Choi ,  Boun Yoon ,  Jae-Jik Baek ,  Byung-Kwon Cho

    发明人： Sukhun Choi ,  Boun Yoon ,  Jae-Jik Baek ,  Byung-Kwon Cho

    IPC分类号： H01L21/28

    CPC分类号： H01L21/32139 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

    摘要： A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.

    摘要翻译： 制造具有金属栅电极的半导体器件的方法包括在具有第一区域和第二区域的半导体衬底上形成绝缘层。 绝缘层形成为包括层间绝缘层和栅极绝缘层。 层间绝缘层具有分别设置在第一和第二区域中的第一和第二沟槽，并且栅极绝缘层至少覆盖第一和第二沟槽的至少底表面。 在具有绝缘层的基板上形成层叠金属层。 在层叠金属层上形成具有非光敏性的平坦化层。 使用干蚀刻工艺选择性地去除第一区域中的平坦化层，以暴露第一区域中的层压金属层，并形成覆盖第二区域中的层叠金属层的平坦化图案。

    Semiconductor devices and methods for manufacturing the same
    5.
    发明授权
    Semiconductor devices and methods for manufacturing the same 有权

    公开(公告)号：US10128336B2

    公开(公告)日：2018-11-13

    申请号：US15009119

    申请日：2016-01-28

    申请人： Sangjine Park ,  Boun Yoon ,  Jeongnam Han

    发明人： Sangjine Park ,  Boun Yoon ,  Jeongnam Han

    IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/78 ,  H01L23/535 ,  H01L29/16 ,  H01L29/165 ,  H01L29/45 ,  H01L29/417

    摘要： Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode.

    Semiconductor Device and Method for Manufacturing the Same
    8.
    发明申请
    Semiconductor Device and Method for Manufacturing the Same 有权
    半导体装置及其制造方法

    公开(公告)号：US20160284806A1

    公开(公告)日：2016-09-29

    申请号：US14989485

    申请日：2016-01-06

    申请人： Sangjine Park ,  Kee Sang Kwon ,  Jae-Jik Baek ,  Boun Yoon

    发明人： Sangjine Park ,  Kee Sang Kwon ,  Jae-Jik Baek ,  Boun Yoon

    IPC分类号： H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L23/31 ,  H01L29/51 ,  H01L29/78 ,  H01L29/06

    CPC分类号： H01L29/41791 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/785

    摘要： A semiconductor device includes an active pattern protruding from a substrate, gate structures crossing over the active pattern, gate spacers on sidewalls of the gate structures, a source/drain region n the active pattern between the gate structures, and a source/drain contact on and connected to the source/drain region. The source/drain contact includes a first portion between the gate structures and being in contact with the gate spacers, a second portion on the first portion and not being in contact with the gate spacers, and a third portion on the second portion. A first boundary between the second and third portions is at the substantially same height as a top surface of the gate structure.

    摘要翻译： 半导体器件包括从衬底突出的有源图案，在有源图案上交叉的栅极结构，栅极结构的侧壁上的栅极间隔物，栅极结构之间的有源图案的源极/漏极区域以及栅极结构之间的源极/漏极接触 并连接到源极/漏极区域。 源极/漏极接触包括在栅极结构之间并与栅极间隔物接触的第一部分，第一部分上的第二部分并且不与栅极间隔物接触，并且在第二部分上具有第三部分。 第二和第三部分之间的第一边界处于与栅极结构的顶表面基本相同的高度。

    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20160064378A1

    公开(公告)日：2016-03-03

    申请号：US14826811

    申请日：2015-08-14

    申请人： Kee Sang KWON ,  Boun Yoon ,  Sangjine Park ,  Myunggeun Song ,  Ki-Hyung Ko ,  Jiwon Yun

    发明人： Kee Sang KWON ,  Boun Yoon ,  Sangjine Park ,  Myunggeun Song ,  Ki-Hyung Ko ,  Jiwon Yun

    IPC分类号： H01L27/088 ,  H01L29/78

    CPC分类号： H01L27/0886 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

    摘要： Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work-function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.

    摘要翻译： 半导体器件可以包括衬底，衬底上的栅极电极以及每个栅极电极的两侧的源极/漏极区域。 每个栅极电极可以包括在基板上的栅极绝缘图案，位于栅极绝缘图案上并具有凹陷的上表面的下部功函电极图案和在凹陷部分上保形延伸的上部功函电极图案 下工作电极图案的上表面。 下部功函电极图案的最表面可以设置在相同的水平，并且上部功函电极图案可以具有彼此不同的厚度。

    SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20120086048A1

    公开(公告)日：2012-04-12

    申请号：US13192939

    申请日：2011-07-28

    申请人： Sangjine Park ,  Boun Yoon ,  Jeongnam Han

    发明人： Sangjine Park ,  Boun Yoon ,  Jeongnam Han

    IPC分类号： H01L29/772

    CPC分类号： H01L29/0847 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/535 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode.

    摘要翻译： 半导体器件和制造半导体器件的方法。 半导体器件包括层叠在半导体衬底上的金属栅电极，栅极绝缘层位于其间，在金属栅电极的两侧设置在半导体衬底上的间隔结构，在两侧形成在半导体衬底中的源/漏区 以及包括覆盖源极/漏极区域的底部部分和从底部部分延伸以覆盖间隔物结构的侧壁的一部分的侧壁部分的蚀刻停止图案，其中侧壁部分的上表面 的蚀刻停止图案位于金属栅电极的上表面下方。