公开(公告)号：US08411477B2

公开(公告)日：2013-04-02

申请号：US12765606

申请日：2010-04-22

申请人： Sanh D. Tang ,  Gurtej S. Sandhu

发明人： Sanh D. Tang ,  Gurtej S. Sandhu

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C11/00 ,  H01L21/82

CPC分类号： G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C7/18 ,  G11C11/4097 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/71 ,  G11C2213/78 ,  H01L27/0688 ,  H01L27/101

摘要： An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.

公开(公告)号：US20130092894A1

公开(公告)日：2013-04-18

申请号：US13275168

申请日：2011-10-17

申请人： Scott E. Sills ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  John Smythe

发明人： Scott E. Sills ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  John Smythe

IPC分类号： H01L47/00

CPC分类号： H01L45/1226 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/085 ,  H01L45/124 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148

摘要： Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first electrode. The trench-shape defines an opening. The programmable material may be configured to reversibly retain a conductive bridge. The memory cell may have an ion source material directly against the programmable material, and may have a second electrode within the opening defined by the trench-shaped programmable material. Some embodiments include arrays of memory cells. The arrays may have first electrically conductive lines, and trench-shaped programmable material structures over the first lines. The trench-shaped structures may define openings within them. Ion source material may be directly against the programmable material, and second electrically conductive lines may be over the ion source material and within the openings defined by the trench-shaped structures.

摘要翻译： 一些实施例包括存储器单元。 存储单元可以具有第一电极和在第一电极上方的沟槽状可编程材料结构。 沟槽形状限定开口。 可编程材料可以被配置为可逆地保持导电桥。 存储单元可以具有直接抵靠可编程材料的离子源材料，并且可以在由沟槽状可编程材料限定的开口内具有第二电极。 一些实施例包括存储器单元阵列。 阵列可以具有第一导电线，以及在第一线上的沟槽状可编程材料结构。 沟槽状结构可以在其内限定开口。 离子源材料可以直接抵靠可编程材料，并且第二导电线可以在离子源材料之上并且在由沟槽状结构限定的开口内。

公开(公告)号：US20110261607A1

公开(公告)日：2011-10-27

申请号：US12765606

申请日：2010-04-22

申请人： Sanh D. Tang ,  Gurtej S. Sandhu

发明人： Sanh D. Tang ,  Gurtej S. Sandhu

IPC分类号： G11C11/00 ,  H01L21/82

CPC分类号： G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C7/18 ,  G11C11/4097 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/71 ,  G11C2213/78 ,  H01L27/0688 ,  H01L27/101

摘要： An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.

摘要翻译： 垂直堆叠层的非易失性交叉点存储单元的阵列包括在存储单元的各个层内的多个水平取向的字线。 具有局部垂直位线延伸的多个水平定向的全局位线延伸穿过多个层。 存储单元的个体包括在水平定向的字线之一和本地垂直位线延伸之一中的一个之间接收的多电阻状态材料，其中这些交叉具有这样的交叉的单个存储器单元的相对的导电电极。 多个位线选择电路单独地电和物理地连接到本地垂直位线延伸的个体，并且被配置为向全局水平位线的个体提供电压电位。 公开了其它实施例和方面。

公开(公告)号：US08427859B2

公开(公告)日：2013-04-23

申请号：US12765598

申请日：2010-04-22

申请人： Gurtej S. Sandhu ,  Sanh D. Tang

发明人： Gurtej S. Sandhu ,  Sanh D. Tang

IPC分类号： G11C11/00 ,  G11C5/02 ,  G11C5/06

CPC分类号： G11C13/0002 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C8/12 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/004 ,  G11C2213/71 ,  H01L27/0688 ,  H01L27/101

摘要： An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.

公开(公告)号：US08362546B2

公开(公告)日：2013-01-29

申请号：US13437406

申请日：2012-04-02

申请人： John Zahurak ,  Sanh D. Tang ,  Gurtej S. Sandhu

发明人： John Zahurak ,  Sanh D. Tang ,  Gurtej S. Sandhu

IPC分类号： H01L29/66

CPC分类号： H01L21/823487 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/105 ,  H01L27/24 ,  H01L29/66666 ,  H01L29/7827

摘要： Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts.

公开(公告)号：US20110261606A1

公开(公告)日：2011-10-27

申请号：US12765598

申请日：2010-04-22

申请人： Gurtej S. Sandhu ,  Sanh D. Tang

发明人： Gurtej S. Sandhu ,  Sanh D. Tang

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0002 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C8/12 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/004 ,  G11C2213/71 ,  H01L27/0688 ,  H01L27/101

摘要： An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.

公开(公告)号：US20110140195A1

公开(公告)日：2011-06-16

申请号：US12635005

申请日：2009-12-10

申请人： John Zahurak ,  Sanh D. Tang ,  Gurtej S. Sandhu

发明人： John Zahurak ,  Sanh D. Tang ,  Gurtej S. Sandhu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823487 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/105 ,  H01L27/24 ,  H01L29/66666 ,  H01L29/7827

摘要： Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts.

摘要翻译： 形成具有支柱的存储器单元阵列和存储单元阵列的方法。 单个柱可以具有由半导体柱上的体半导体材料和牺牲帽形成的半导体柱。 源区可以在柱的列之间，并且栅极线沿着柱柱延伸并且与相应的源极区域间隔开。 每个栅极线沿着一列柱围绕半导体柱的一部分。 可以选择性地去除牺牲帽结构，从而形成露出相应半导体柱的顶部的自对准开口。 形成在自对准开口中的单独的漏极触点电连接到相应的半导体柱。

公开(公告)号：US08536561B2

公开(公告)日：2013-09-17

申请号：US13275168

申请日：2011-10-17

申请人： Scott E. Sills ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  John Smythe

发明人： Scott E. Sills ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  John Smythe

IPC分类号： H01L47/00

CPC分类号： H01L45/1226 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/085 ,  H01L45/124 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148

摘要： Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first electrode. The trench-shape defines an opening. The programmable material may be configured to reversibly retain a conductive bridge. The memory cell may have an ion source material directly against the programmable material, and may have a second electrode within the opening defined by the trench-shaped programmable material. Some embodiments include arrays of memory cells. The arrays may have first electrically conductive lines, and trench-shaped programmable material structures over the first lines. The trench-shaped structures may define openings within them. Ion source material may be directly against the programmable material, and second electrically conductive lines may be over the ion source material and within the openings defined by the trench-shaped structures.

公开(公告)号：US20120193703A1

公开(公告)日：2012-08-02

申请号：US13437406

申请日：2012-04-02

申请人： John Zahurak ,  Sanh D. Tang ,  Gurtej S. Sandhu

发明人： John Zahurak ,  Sanh D. Tang ,  Gurtej S. Sandhu

IPC分类号： H01L29/78

CPC分类号： H01L21/823487 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/105 ,  H01L27/24 ,  H01L29/66666 ,  H01L29/7827

摘要： Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts.

摘要翻译： 形成具有支柱的存储器单元阵列和存储单元阵列的方法。 单个柱可以具有由半导体柱上的体半导体材料和牺牲帽形成的半导体柱。 源区可以在柱的列之间，并且栅极线沿着柱柱延伸并且与相应的源极区域间隔开。 每个栅极线沿着一列柱围绕半导体柱的一部分。 可以选择性地去除牺牲帽结构，从而形成露出相应半导体柱的顶部的自对准开口。 形成在自对准开口中的单独的漏极触点电连接到相应的半导体柱。

公开(公告)号：US08148222B2

公开(公告)日：2012-04-03

申请号：US12635005

申请日：2009-12-10

申请人： John Zahurak ,  Sanh D. Tang ,  Gurtej S. Sandhu

发明人： John Zahurak ,  Sanh D. Tang ,  Gurtej S. Sandhu

IPC分类号： H01L21/8238

CPC分类号： H01L21/823487 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/105 ,  H01L27/24 ,  H01L29/66666 ,  H01L29/7827

摘要： Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts.

摘要翻译： 形成具有支柱的存储器单元阵列和存储单元阵列的方法。 单个柱可以具有由半导体柱上的体半导体材料和牺牲帽形成的半导体柱。 源区可以在柱的列之间，并且栅极线沿着柱柱延伸并且与相应的源极区域间隔开。 每个栅极线沿着一列柱围绕半导体柱的一部分。 可以选择性地去除牺牲帽结构，从而形成露出相应半导体柱的顶部的自对准开口。 形成在自对准开口中的单独的漏极触点电连接到相应的半导体柱。