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    Nanowire field effect transistors
    1.
    发明授权
    Nanowire field effect transistors 有权
    纳米线场效应晶体管

    公开(公告)号：US08648330B2

    公开(公告)日：2014-02-11

    申请号：US13343799

    申请日：2012-01-05

    申请人： Sarunya Bangsaruntip ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

    IPC分类号： H01L27/12 ,  H01L21/335 ,  B82Y40/00 ,  B82Y99/00

    CPC分类号： H01L29/42392 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

    摘要： A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region.

    摘要翻译： 形成纳米线场效应晶体管（FET）器件的方法包括在衬底上形成纳米线，在纳米线的一部分周围形成衬垫材料，在衬垫材料上形成覆盖层，形成邻近 覆盖层和纳米线的周围部分，在覆盖层和第一间隔物上形成硬掩模层，去除纳米线的暴露部分以形成由栅极材料部分限定的第一空腔，在暴露的杂交上外延生长半导体材料 在所述第一空腔中的所述纳米线的截面，去除所述硬掩模层和所述覆盖层，在所述第一空腔中外延生长的所述半导体材料周围形成第二覆盖层，以限定沟道区，以及形成与所述第二覆盖层接触的源极区和漏极区 渠道区域。

    Nanowire field effect transistors
    2.
    发明授权
    Nanowire field effect transistors 有权
    纳米线场效应晶体管

    公开(公告)号：US08558219B2

    公开(公告)日：2013-10-15

    申请号：US13606365

    申请日：2012-09-07

    申请人： Sarunya Bangsaruntip ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

    IPC分类号： H01L21/335 ,  B82Y40/00 ,  B82Y99/00

    CPC分类号： H01L29/42392 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

    摘要： A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region.

    摘要翻译： 形成纳米线场效应晶体管（FET）器件的方法包括在衬底上形成纳米线，在纳米线的一部分周围形成衬垫材料，在衬垫材料上形成覆盖层，形成邻近 覆盖层和纳米线的周围部分，在覆盖层和第一间隔物上形成硬掩模层，去除纳米线的暴露部分以形成由栅极材料部分限定的第一空腔，在暴露的杂交上外延生长半导体材料 在所述第一空腔中的所述纳米线的截面，去除所述硬掩模层和所述覆盖层，在所述第一空腔中外延生长的所述半导体材料周围形成第二覆盖层，以限定沟道区，以及形成与所述第二覆盖层接触的源极区和漏极区 渠道区域。

    Nanowire Circuits in Matched Devices
    4.
    发明申请
    Nanowire Circuits in Matched Devices 有权
    匹配器件中的纳米线电路

    公开(公告)号：US20120280206A1

    公开(公告)日：2012-11-08

    申请号：US13554057

    申请日：2012-07-20

    申请人： Sarunya Bangsaruntip ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

    IPC分类号： H01L27/085 ,  H01L21/8232

    CPC分类号： H03K19/20 ,  B82Y10/00 ,  G11C11/412 ,  G11C11/54 ,  H01L27/092 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/12 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/78696

    摘要： A memory device includes a first nanowire connected to a first bit line node and a ground node, a first field effect transistor (FET) having a gate disposed on the first nanowire, a second FET having a gate disposed on the first nanowire, a second nanowire connected to a voltage source node and a first input node, a third FET having a gate disposed on the second nanowire, a third nanowire connected to the voltage source node and a second input node, a fourth FET having a gate disposed on the third nanowire, a fourth nanowire connected to a second bit line node and the ground node, a fifth FET having a gate disposed on the fourth nanowire, and a sixth FET having a gate disposed on the fourth nanowire.

    摘要翻译： 存储器件包括连接到第一位线节点和接地节点的第一纳米线，具有设置在第一纳米线上的栅极的第一场效应晶体管（FET），具有设置在第一纳米线上的栅极的第二FET， 连接到电压源节点和第一输入节点的纳米线，具有设置在第二纳米线上的栅极的第三FET，连接到电压源节点的第三纳米线和第二输入节点，具有设置在第三纳米线上的栅极的第四FET 纳米线，连接到第二位线节点的第四纳米线和所述接地节点，具有设置在所述第四纳米线上的栅极的第五FET以及设置在所述第四纳米线上的栅极的第六FET。

    Maskless process for suspending and thinning nanowires
    6.
    发明授权
    Maskless process for suspending and thinning nanowires 有权
    用于悬浮和稀化纳米线的无掩模工艺

    公开(公告)号：US07884004B2

    公开(公告)日：2011-02-08

    申请号：US12365623

    申请日：2009-02-04

    申请人： Sarunya Bangsaruntip ,  Guy Cohen ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy Cohen ,  Jeffrey W. Sleight

    IPC分类号： H01L21/00

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02667 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696 ,  Y10S977/762

    摘要： Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.

    摘要翻译： 提供了基于半导体的电子器件及其制造技术。 在一个方面，提供了一种包括第一垫的装置; 第二焊盘和多个纳米线，其以形成在掩埋氧化物（BOX）层上的绝缘体上硅（SOI）层中的梯形结构连接第一焊盘和第二焊盘，该纳米线具有一个或多个维度 由硅从纳米线重新分配到焊盘。 该器件可以包括具有围绕纳米线的栅极的场效应晶体管（FET），其中纳米线的部分由FET的栅极沟道围绕，第一焊盘和纳米线的部分从邻近第一 焊盘形成FET的源极区域，并且第二焊盘和从与第二焊盘相邻的栅极延伸出的纳米线的部分形成FET的漏极区域。

    Nanowire circuits in matched devices
    9.
    发明授权
    Nanowire circuits in matched devices 有权
    纳米线电路在匹配的设备

    公开(公告)号：US08520430B2

    公开(公告)日：2013-08-27

    申请号：US13554057

    申请日：2012-07-20

    申请人： Sarunya Bangsaruntip ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

    IPC分类号： G11C11/00

    CPC分类号： H03K19/20 ,  B82Y10/00 ,  G11C11/412 ,  G11C11/54 ,  H01L27/092 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/12 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/78696

    摘要： A memory device includes a first nanowire connected to a first bit line node and a ground node, a first field effect transistor (FET) having a gate disposed on the first nanowire, a second FET having a gate disposed on the first nanowire, a second nanowire connected to a voltage source node and a first input node, a third FET having a gate disposed on the second nanowire, a third nanowire connected to the voltage source node and a second input node, a fourth FET having a gate disposed on the third nanowire, a fourth nanowire connected to a second bit line node and the ground node, a fifth FET having a gate disposed on the fourth nanowire, and a sixth FET having a gate disposed on the fourth nanowire.

    摘要翻译： 存储器件包括连接到第一位线节点和接地节点的第一纳米线，具有设置在第一纳米线上的栅极的第一场效应晶体管（FET），具有设置在第一纳米线上的栅极的第二FET， 连接到电压源节点和第一输入节点的纳米线，具有设置在第二纳米线上的栅极的第三FET，连接到电压源节点的第三纳米线和第二输入节点，具有设置在第三纳米线上的栅极的第四FET 纳米线，连接到第二位线节点的第四纳米线和所述接地节点，具有设置在所述第四纳米线上的栅极的第五FET以及设置在所述第四纳米线上的栅极的第六FET。