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    Frame buffer architecture capable of accessing a pixel aligned M by N array of pixels on the screen of an attached monitor
    1.
    发明授权
    Frame buffer architecture capable of accessing a pixel aligned M by N array of pixels on the screen of an attached monitor 失效
    帧缓冲器架构能够访问在附加的监视器的屏幕上由N个像素阵列对齐的像素

    公开(公告)号：US4903217A

    公开(公告)日：1990-02-20

    申请号：US13843

    申请日：1987-02-12

    申请人： Satish Gupta ,  Leon Lumelsky ,  Marc Segre

    发明人： Satish Gupta ,  Leon Lumelsky ,  Marc Segre

    IPC分类号： G06F12/00 ,  G06F3/153 ,  G06F12/06 ,  G06T1/60 ,  G09G5/39

    CPC分类号： G09G5/39 ,  G09G2360/123

    摘要： A frame buffer memory organization which is capable of accessing a pixel aligned M by N array of contiguous pixels on the screen from a frame buffer memory constructed of an M by N array of memory chips by driving a common address bus to all the memory chips, and by driving N RAS wires horizontally across the memory chip array and M CAS wires vertically down the memory chip array. The writing of individual pixels in this array is enabled by energizing the write enable pins to each memory chip directly.The data wires in the memory organization are tied together such that M horizontal pixels in a single row can be read or written simultaneously. Additionally, all M and N pixels may be written simultaneously if the data in all vertical columns is the same.The frame buffer includes a selectively energizable plane mask for disabling desired planes of accessed pixels.By sequentially controlling the output enables to the different rows of the addressed M by N array, the frame buffer can provide rapid access to N-1 rows after normally accessing the first one.The described architecture will work equally well for M by N other array organizations with a different size (e.g., 8 by 8, 3 by 4, 5 by 4, etc). These other configurations would of course require as many concurrently accessable memory chips or sections as there are pixels in the accessed rectangular array as will be well understood.

    Computer memory system with integrated parallel shift circuits
    5.
    发明授权
    Computer memory system with integrated parallel shift circuits 失效
    具有集成并行移位电路的计算机存储系统

    公开(公告)号：US4644503A

    公开(公告)日：1987-02-17

    申请号：US567215

    申请日：1983-12-30

    申请人： David F. Bantz ,  Satish Gupta ,  Bruce D. Lucas

    发明人： David F. Bantz ,  Satish Gupta ,  Bruce D. Lucas

    IPC分类号： G09G5/39 ,  G06F12/00 ,  G06F12/06 ,  G06T1/60 ,  G06T3/60 ,  G09G1/02 ,  G09G5/00 ,  G09G5/38 ,  G09G5/395 ,  G11C7/10 ,  G11C11/401 ,  G11C13/00

    CPC分类号： G11C7/1006 ,  G09G1/02

    摘要： The system includes a plurality of memory units each for storing a plurality of independently addressable binary bits. The units operate together in response to each common bit address to supply a bit from each unit to form an array of bits for a discrete section of a larger array. The units are interconnected through common interconnection buses and selectively actuable input and output gate connections to those buses to provide for selective shifting of bits between units to change the bit array.

    摘要翻译： 该系统包括多个存储单元，每个存储单元用于存储多个可独立寻址的二进制位。 这些单元响应于每个公共位地址一起工作以从每个单元提供一个位，以形成用于较大阵列的离散部分的位阵列。 这些单元通过公共互连总线和可选择地致动的输入和输出门连接到这些总线互连，以提供单元之间的位的选择性移位以改变位阵列。

    Virtual resolution displays
    6.
    发明授权
    Virtual resolution displays 失效
    虚拟分辨率显示

    公开(公告)号：US4720705A

    公开(公告)日：1988-01-19

    申请号：US775570

    申请日：1985-09-13

    申请人： Satish Gupta ,  Bruce D. Lucas

    发明人： Satish Gupta ,  Bruce D. Lucas

    IPC分类号： G06F3/153 ,  G09G1/00 ,  G09G5/26 ,  G09G5/28 ,  G09G1/06

    CPC分类号： G09G5/28 ,  G09G1/002

    摘要： A method for improving the viewing quality of a CRT display image without increasing resolution of the display. With the invention disclosed herein, characters are apparently positioned at sub-pixel locations to improve the viewing quality of a CRT display image. This apparent positioning is accomplished by changing intensity values assigned to pixels on a CRT display. In the preferred embodiment, the change in intensity values is effected by linear interpolation with intensity values of neighboring pixels to yield second intensity values. These second intensity values, then, improve the viewing quality of the CRT display image.

    摘要翻译： 一种用于提高CRT显示图像的观看质量而不增加显示分辨率的方法。 利用本文公开的发明，字符显然位于子像素位置以改善CRT显示图像的观看质量。 这种明显的定位是通过改变分配给CRT显示器上的像素的强度值来实现的。 在优选实施例中，强度值的变化通过对相邻像素的强度值的线性插值来实现，以产生第二强度值。 然后，这些第二强度值提高了CRT显示图像的观看质量。

    Random address memory with fast clear
    8.
    发明授权
    Random address memory with fast clear 失效
    随机地址内存快速清晰

    公开(公告)号：US4587629A

    公开(公告)日：1986-05-06

    申请号：US567301

    申请日：1983-12-30

    申请人： Frederick H. Dill ,  Satish Gupta ,  Peter J. Warter

    发明人： Frederick H. Dill ,  Satish Gupta ,  Peter J. Warter

    IPC分类号： G11C11/401 ,  G11C7/20 ,  G06F12/00

    CPC分类号： G11C7/20

    摘要： A technique and apparatus for augmenting a random access memory with a fast clear or reset mechanism are described. A dynamic RAM having a fast clear mechanism in accordance with the present invention includes means for coupling a digital signal onto all bit lines; and fast reset control means operative for energizing the coupling means for connecting the digital signal to all of the bit lines such that upon energizing of a selected word line, all the bits connected to the selected word line are reset to the state of the digital signal, whereby reset time of the random access memory is reduced. The present invention is especially beneficial for incorporation in a frame buffer of an all points addressable raster scan display, and in a page buffer of an all points addressable printer wherein there is a requirement for high update performance.

    摘要翻译： 描述了用于利用快速清除或复位机制来增加随机存取存储器的技术和装置。 具有根据本发明的快速清除机制的动态RAM包括用于将数字信号耦合到所有位线上的装置; 并且快速复位控制装置用于激励用于将数字信号连接到所有位线的耦合装置，使得在激励所选字线时，连接到所选字线的所有位被复位到数字信号的状态 从而减少随机存取存储器的复位时间。 本发明特别有利于结合在所有点可寻址光栅扫描显示器的帧缓冲器中，并且在需要高更新性能的全点可寻址打印机的页缓冲器中。

    Method of producing shaped articles of fiber/binder mixtures
    9.
    发明授权
    Method of producing shaped articles of fiber/binder mixtures 失效
    生产纤维/粘合剂混合物的成型制品的方法

    公开(公告)号：US5102596A

    公开(公告)日：1992-04-07

    申请号：US620402

    申请日：1990-11-29

    申请人： Karsten Lempfer ,  Satish Gupta

    发明人： Karsten Lempfer ,  Satish Gupta

    IPC分类号： B27N1/02 ,  B28B1/52 ,  B28B17/02 ,  C04B28/02 ,  D21J3/00

    CPC分类号： D21J3/00 ,  B28B1/525 ,  B28B17/02 ,  C04B28/04 ,  C04B28/14 ,  C04B2111/00612 ,  Y02W30/97

    摘要： Paper or cellulose pieces forming a fiber raw material are wetted with water prior to comminution so that the comminution into fibers is effected with the moistened raw material. The moisture content of the fibers makes up at least part of the water of hydration required to completely set the binder which is mixed with the fibers. The binder can be plaster (gypsum) or hydraulic cement. The mixture is pressed to the desired shape and heat may be applied.

    摘要翻译： 形成纤维原料的纸或纤维素片在粉碎之前用水润湿，以便用润湿的原料进行粉碎成纤维。 纤维的水分含量构成了完全固化与纤维混合的粘合剂所需的水合水的至少一部分。 粘合剂可以是石膏（石膏）或水硬性水泥。 将混合物压制成所需的形状并施加热量。