公开(公告)号：US06927442B2

公开(公告)日：2005-08-09

申请号：US10329722

申请日：2002-12-26

申请人： Satoru Kaneko ,  Toshiyuki Ohkoda ,  Takao Myono

发明人： Satoru Kaneko ,  Toshiyuki Ohkoda ,  Takao Myono

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/08 ,  H01L27/092 ,  H02M3/07 ,  H01L29/72

CPC分类号： H01L27/0921 ,  H01L27/0623 ,  H02M3/07 ,  H02M3/073

摘要： A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and P-type well regions are formed in the second epitaxial silicon layer. P+-type buried layers abutting on bottoms of the P-type well regions and N+-type buried layers abutting on bottoms of the P+-type buried layers and electrically isolating the P-type well regions from the single crystalline silicon substrate are formed. An MOS transistor is formed in each of the P-type well regions and a drain layer of the MOS transistor and each of the P-type well regions are electrically connected.

摘要翻译： 提供了适用于提供大电流容量并防止发生闩锁的用于电荷泵装置的半导体器件。 在P型单晶硅衬底上堆叠第一和第二N型外延硅层，在第二外延硅层中形成P型阱区。 邻接在P型阱区域的底部上的P +型掩埋层和与P +型掩埋层的底部邻接并与P型阱区域与单晶硅衬底电隔离的N +型掩埋层。 在每个P型阱区和MOS晶体管的漏极层中形成MOS晶体管，并且每个P型阱区电连接。

公开(公告)号：US06881997B2

公开(公告)日：2005-04-19

申请号：US10329718

申请日：2002-12-26

申请人： Satoru Kaneko ,  Toshiyuki Ohkoda ,  Takao Myono

发明人： Satoru Kaneko ,  Toshiyuki Ohkoda ,  Takao Myono

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H02M3/07 ,  H01L27/108

CPC分类号： H02M3/073 ,  H01L27/0222 ,  H01L27/0623 ,  H01L27/0928 ,  H02M2003/075 ,  H02M2003/078

摘要： In a charge pump device, occurrence of a latch up can be prevented and current capacity can be increased. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, P-type well regions are formed in the N-type epitaxial silicon layer separated from each other, and P-type lower isolation layers and P-type upper isolation layers are formed between the P-type well regions. Then a charge transfer MOS transistor is formed in each of the P-type well regions. The P-type single crystalline silicon substrate is biased to a ground potential or a negative potential.

摘要翻译： 在电荷泵装置中，可以防止闩锁的发生，并且可以增加电流容量。 在P型单晶硅衬底上形成N型外延硅层，在分离的N型外延硅层中形成P型阱区，P型下隔离层和P型 在P型阱区之间形成上隔离层。 然后在每个P型阱区中形成电荷转移MOS晶体管。 P型单晶硅衬底被偏压到接地电位或负电位。

公开(公告)号：US06864543B2

公开(公告)日：2005-03-08

申请号：US10329643

申请日：2002-12-26

申请人： Satoru Kaneko ,  Toshiyuki Ohkoda ,  Takao Myono

发明人： Satoru Kaneko ,  Toshiyuki Ohkoda ,  Takao Myono

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/02 ,  H01L27/06 ,  H01L27/08 ,  H01L27/092 ,  H02M3/07 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H02M3/073 ,  H01L27/0222 ,  H01L27/0623 ,  H01L27/0921

摘要： A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and a P-type well region is formed in the second epitaxial silicon layer. A P+-type buried layer is formed abutting on a bottom of the P-type well region, and an MOS transistor is formed in the P-type well region. The MOS transistor has a first source layer N+S of high impurity concentration, a first drain layer N+D of high impurity concentration and a second source layer N−S and/or a second drain layer N−D of low impurity concentration, which is diffused deeper than the first source layer N+S of high impurity concentration and the first drain layer N+D of high impurity concentration.

摘要翻译： 提供了适用于提供大电流容量并防止发生闩锁的用于电荷泵装置的半导体器件。 第一和第二N型外延硅层堆叠在P型单晶硅衬底上，并且在第二外延硅层中形成P型阱区。 在P型阱区的底部形成P +型掩埋层，在P型阱区中形成MOS晶体管。 MOS晶体管具有高杂质浓度的第一源极层N + S，高杂质浓度的第一漏极层N + D和低杂质浓度的第二源极层NS和/或第二漏极层ND，其被扩散更深 高杂质浓度的第一源极层N + S和杂质浓度高的第一漏极层N + D。

公开(公告)号：US06822298B2

公开(公告)日：2004-11-23

申请号：US10329851

申请日：2002-12-26

申请人： Satoru Kaneko ,  Toshiyuki Ohkoda ,  Takao Myono

发明人： Satoru Kaneko ,  Toshiyuki Ohkoda ,  Takao Myono

IPC分类号： H01L2976

CPC分类号： H01L21/823892 ,  H01L21/8249 ,  H01L27/0222 ,  H01L27/0623 ,  H01L27/0921

摘要： A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, and a P-type well region is formed in the N-type epitaxial silicon layer. A P+-type buried layer abutting on a bottom of the P-type well region and an N+-type buried layer partially overlapping with the P+-type buried layer and electrically isolating the P-type well region from the single crystalline silicon substrate are formed. And then, an MOS transistor is formed in the P-type well region.

摘要翻译： 提供了适用于提供大电流容量并防止发生闩锁的用于电荷泵装置的半导体器件。 在P型单晶硅衬底上形成N型外延硅层，在N型外延硅层中形成P型阱区。 形成邻接在P型阱区的底部的P +型掩埋层和与P +型掩埋层部分重叠并将P型阱区与单晶硅衬底电隔离的N +型掩埋层 。 然后，在P型阱区域中形成MOS晶体管。

公开(公告)号：US20050056898A1

公开(公告)日：2005-03-17

申请号：US10969625

申请日：2004-10-20

申请人： Satoru Kaneko ,  Toshiyuki Ohkoda ,  Takao Myono

发明人： Satoru Kaneko ,  Toshiyuki Ohkoda ,  Takao Myono

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H03K19/0185 ,  H01L29/76

CPC分类号： H01L21/823892 ,  H01L21/8249 ,  H01L27/0222 ,  H01L27/0623 ,  H01L27/0921

摘要： A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, and a P-type well region is formed in the N-type epitaxial silicon layer. A P+-type buried layer abutting on a bottom of the P-type well region and an N+-type buried layer partially overlapping with the P+-type buried layer and electrically isolating the P-type well region from the single crystalline silicon substrate are formed. And then, an MOS transistor is formed in the P-type well region.

摘要翻译： 提供了适用于提供大电流容量并防止发生闩锁的用于电荷泵装置的半导体器件。 在P型单晶硅衬底上形成N型外延硅层，在N型外延硅层中形成P型阱区。 形成邻接在P型阱区的底部的P +型掩埋层和与P +型掩埋层部分重叠并将P型阱区与单晶硅衬底电隔离的N +型掩埋层 。 然后，在P型阱区域中形成MOS晶体管。

公开(公告)号：US06864525B2

公开(公告)日：2005-03-08

申请号：US10329842

申请日：2002-12-26

申请人： Satoru Kaneko ,  Toshiyuki Ohkoda ,  Takao Myono

发明人： Satoru Kaneko ,  Toshiyuki Ohkoda ,  Takao Myono

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/02 ,  H01L27/06 ,  H02M3/07 ,  H01L29/72

CPC分类号： H01L27/0218 ,  H01L27/0623 ,  H02M3/073

摘要： A latch up in a charge pump device is prevented as well as a withstand voltage of an MOS transistor used in the charge pump device is increased with this invention. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and P-type well regions are formed in the second epitaxial silicon layer separated from each other. A P-type isolation layer is formed between the P-type well regions. A P+-type buried layer is formed abutting on a bottom of each of the well regions, an N+-type buried layer is formed abutting on a bottom of the P+-type buried layer, and a transistor for charge transfer is formed in each of the P-type well regions.

摘要翻译： 防止电荷泵装置中的闩锁，并且通过本发明，电荷泵装置中使用的MOS晶体管的耐受电压也增加。 在P型单晶硅衬底上堆叠第一和第二N型外延硅层，并且在彼此分离的第二外延硅层中形成P型阱区。 在P型阱区之间形成P型隔离层。 形成邻接在每个阱区的底部的P +型掩埋层，在P +型掩埋层的底部邻接形成N +型掩埋层，并且在每个中形成电荷转移用晶体管 P型井区。

公开(公告)号：US5747375A

公开(公告)日：1998-05-05

申请号：US673052

申请日：1996-07-01

申请人： Satoru Kaneko ,  Toshiyuki Ohkoda

发明人： Satoru Kaneko ,  Toshiyuki Ohkoda

IPC分类号： H01L21/02 ,  H01L21/20

CPC分类号： H01L28/40

摘要： A method of manufacturing a semiconductor integrated circuit device employs a new reflowing process of an insulating film having contact holes and openings therethrough. A good step coverage of a wiring electrode at the contact holes of the insulating film can be obtained with reduced thermal cycles in the manufacturing of integrated circuit devices, and also with a reduced heat treatment temperature of the reflowing process. The process includes a step of depositing a silicon nitride film on the insulating film and on the contact holes by chemical vapor deposition at a temperature between 700.degree. C. and 800.degree. C. so as to deform edges of the contact holes in the insulating film to be rounded and smooth.

摘要翻译： 半导体集成电路器件的制造方法采用具有接触孔和开口的绝缘膜的新的回流工艺。 在集成电路器件的制造中，可以获得在绝缘膜的接触孔处的布线电极的良好的阶梯覆盖，并且还具有降低的回流工艺的热处理温度。 该方法包括通过在700℃至800℃之间的温度下通过化学气相沉积在绝缘膜上和接触孔上沉积氮化硅膜的步骤，以使绝缘膜中接触孔的边缘变形 圆润光滑。

公开(公告)号：US5565699A

公开(公告)日：1996-10-15

申请号：US509749

申请日：1995-08-13

申请人： Satoru Kaneko ,  Toshiyuki Ohkoda

发明人： Satoru Kaneko ,  Toshiyuki Ohkoda

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L28/40

摘要： A semiconductor integrated circuit device can prevent a crack in a silicon nitride layer acting as a dielectric thin film of a capacitance element. A lower electrode of a gate polycrystalline silicon is formed on a LOCOS oxide film. A BPSG film is formed as an interlayer insulating film. An opening as well as first and second contact holes surrounding the opening are formed. A silicon nitride film is deposited on the opening and then an upper electrode is formed on the silicon nitride film. A take-out electrode extending out of the first contact hole is in contact with the lower electrode. The first and second contact holes separate the BPSG film into a first portion surrounding the silicon nitride film and a second portion outside the first portion.

摘要翻译： 半导体集成电路器件可以防止用作电容元件的电介质薄膜的氮化硅层中的裂纹。 在LOCOS氧化膜上形成栅多晶硅的下电极。 形成BPSG膜作为层间绝缘膜。 形成开口以及围绕开口的第一和第二接触孔。 在开口上沉积氮化硅膜，然后在氮化硅膜上形成上电极。 从第一接触孔延伸出的取出电极与下电极接触。 第一和第二接触孔将BPSG膜分离成围绕氮化硅膜的第一部分和第一部分外部的第二部分。

公开(公告)号：US5395782A

公开(公告)日：1995-03-07

申请号：US922065

申请日：1992-07-29

申请人： Toshiyuki Ohkoda ,  Satoru Kaneko

发明人： Toshiyuki Ohkoda ,  Satoru Kaneko

IPC分类号： H01L21/316 ,  H01L21/318 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L21/28 ,  H01L21/62

CPC分类号： H01L21/8249 ,  H01L27/0635

摘要： A LOCOS film is formed on the surface of an epitaxial layer. A gate electrode is formed on the epitaxial layer. At the same time that the gate electrode is formed, a lower electrode is formed on the LOCOS film. A diffusion region is formed on each element and then covered with a BPSG film. A contact hole and capacitor exposure are formed in a capacitor element simultaneously. A film of SiN is deposited in layers over the capacitor exposure. The film of SiN covers undesired areas about the capacitor exposure. Excess SiN film outside the desired area over the capacitor exposure is removed by masking and etching to leave the remaining film area over the capacitor exposure to serve as a capacitor dielectric film. Finally, an Al upper electrode is formed over the SiN film to serve as electrode wiring. The process reduces the series resistance of the capacitor element, thereby reducing power required for charging the dielectric, and speeding the charging process. The low resistance eliminates parasitic leakage currents and the formation of parasitic capacitances.

摘要翻译： 在外延层的表面上形成LOCOS膜。 在外延层上形成栅电极。 在形成栅电极的同时，在LOCOS膜上形成下电极。 在每个元件上形成扩散区，然后用BPSG膜覆盖。 在电容器元件中同时形成接触孔和电容器的暴露。 在电容器曝光层上沉积SiN膜。 SiN膜覆盖电容器曝光的不希望的区域。 通过掩模和蚀刻去除在电容器曝光之后的期望区域之外的过量SiN膜，以使剩余的膜面积超过电容器曝光以用作电容器电介质膜。 最后，在SiN膜上形成Al上电极，作为电极配线。 该过程降低了电容器元件的串联电阻，从而降低了对电介质充电所需的功率，并加速了充电过程。 低电阻消除寄生漏电流和寄生电容的形成。

公开(公告)号：US06566728B1

公开(公告)日：2003-05-20

申请号：US09678555

申请日：2000-10-04

申请人： Shigeaki Okawa ,  Toshiyuki Ohkoda ,  Yoshiaki Ohbayashi ,  Mamoru Yasuda ,  Shinichi Saeki ,  Shuji Osawa

发明人： Shigeaki Okawa ,  Toshiyuki Ohkoda ,  Yoshiaki Ohbayashi ,  Mamoru Yasuda ,  Shinichi Saeki ,  Shuji Osawa

IPC分类号： H01L2900

CPC分类号： H04R19/005 ,  H04R19/04

摘要： First, a stationary electrode layer is formed over a semiconductor substrate and an integrated network is composed in a circuit element area around the stationary electrode layer by electrode wiring forming each circuit element. A spacer is arranged on a passivation film in plural places. A dummy island is formed in an area between the circuit element area and the stationary electrode layer area. Supply potential Vcc is applied to the dummy island and ground potential GND is applied to a P+-type separated area.

摘要翻译： 首先，在半导体衬底上形成固定电极层，并且通过形成每个电路元件的电极布线，在固定电极层周围的电路元件区域中形成集成网络。 在多个位置上在隔离膜上设置间隔物。 在电路元件区域和固定电极层区域之间的区域中形成虚设的岛。 将供电电位Vcc施加到虚拟岛，将接地电位GND施加到P +型分离区域。