公开(公告)号：US5636366A

公开(公告)日：1997-06-03

申请号：US549889

申请日：1995-10-30

申请人： Scott G. Robinson ,  Richard L. Sites ,  Richard T. Witek

发明人： Scott G. Robinson ,  Richard L. Sites ,  Richard T. Witek

IPC分类号： G06F9/38 ,  G06F9/44 ,  G06F9/45 ,  G06F9/455 ,  G06F13/00

CPC分类号： G06F8/30 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/30174 ,  G06F9/3834 ,  G06F9/3861 ,  G06F9/45504

摘要： A system or method is provided for translating a first program code to a second program code and for executing the second program code while preserving instruction state-atomicity of the first code. The first program code is executable on a computer having a first architecture adapted to a first instruction set and the second program code is executable on a computer having a memory and register state and a second architecture adapted to a second instruction set that is reduced relative to the first instruction set.A first computer translates the first code instructions to corresponding second code instructions in accordance with a pattern code that defines first code instructions in terms of second code instructions. The second code instructions for each first code instruction organized in a granular instruction sequence having in order at least two groups, a first group having a first subgroup including second code read instructions and a second subgroup including modify instructions and a second group having a third subgroup including state update instructions subject to exception, including any special write instruction required to implement the first code instruction being translated, and a fourth subgroup including state update instructions free of exception.

摘要翻译： 提供了一种用于将第一程序代码转换为第二程序代码并用于执行第二程序代码同时保持第一代码的指令状态原子性的系统或方法。 第一程序代码可在具有适于第一指令集的第一架构的计算机上执行，并且第二程序代码可在具有存储器和寄存器状态的计算机上执行，以及适于相对于第二指令集减少的第二指令集的第二架构 第一个指令集 第一计算机根据第二代码指令定义第一代码指令的模式代码将第一代码指令转换为对应的第二代码指令。 按照具有至少两组的粒度指令序列组织的每个第一代码指令的第二代码指令，第一组具有包括第二代码读指令的第一子组和包括修改指令的第二子组，以及具有第三子组的第二组 包括受异常的状态更新指令，包括实现要转换的第一代码指令所需的特殊写入指令，以及包括状态更新指令的第四子组。

公开(公告)号：US5410682A

公开(公告)日：1995-04-25

申请号：US289025

申请日：1994-08-10

申请人： Richard L. Sites ,  Richard T. Witek

发明人： Richard L. Sites ,  Richard T. Witek

IPC分类号： G06F9/30 ,  G06F9/308 ,  G06F9/312 ,  G06F9/38 ,  G06F12/04 ,  G06F15/76

CPC分类号： G06F12/1027 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30054 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3816 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861 ,  G06F2212/652

摘要： A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes.

摘要翻译： RISC（精简指令集）类型的高性能CPU采用标准化的固定指令大小，并且仅允许简化的存储器访问数据宽度和寻址模式。 指令集仅限于寄存器到寄存器操作和寄存器加载/存储操作。 包括允许使用先前建立的数据结构的字节操作指令包括进行寄存器中字节提取，插入和屏蔽以及非对齐加载和存储指令的功能。 提供加载/锁定和存储/条件指令允许实现原子字节写入。

公开(公告)号：US5193167A

公开(公告)日：1993-03-09

申请号：US547618

申请日：1990-06-29

申请人： Richard L. Sites ,  Richard T. Witek

发明人： Richard L. Sites ,  Richard T. Witek

IPC分类号： G06F9/305 ,  G06F9/30 ,  G06F9/38 ,  G06F15/16 ,  G06F15/177

CPC分类号： G06F9/383 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087

摘要： A high performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes.

公开(公告)号：US5454091A

公开(公告)日：1995-09-26

申请号：US111284

申请日：1993-08-24

申请人： Richard L. Sites ,  Richard T. Witek

发明人： Richard L. Sites ,  Richard T. Witek

IPC分类号： G06F9/34 ,  G06F12/10

CPC分类号： G06F12/1027 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F2212/652

摘要： A high-performance central processing unit (CPU) of the reduced instruction set (RISC) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. The processor can employ a variable memory page size, so that the entries in a translation buffer for implementing virtual addressing can be optimally used. A granularity hint is added to the page table entry to define the page size for this entry.

摘要翻译： 精简指令集（RISC）类型的高性能中央处理单元（CPU）采用标准化的固定指令大小，仅允许简化的存储器访问数据宽度和寻址模式。 指令集仅限于寄存器到寄存器操作和寄存器加载/存储操作。 处理器可以采用可变存储器页面大小，使得可以最佳地使用用于实现虚拟寻址的翻译缓冲器中的条目。 在页表项中添加了粒度提示，以定义此条目的页面大小。

公开(公告)号：US5469551A

公开(公告)日：1995-11-21

申请号：US251626

申请日：1994-05-31

申请人： Richard L. Sites ,  Richard T. Witek

发明人： Richard L. Sites ,  Richard T. Witek

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F9/315 ,  G06F15/76

CPC分类号： G06F9/3004 ,  G06F9/30032 ,  G06F9/30054 ,  G06F9/30072 ,  G06F9/324 ,  G06F9/342 ,  G06F9/3804 ,  G06F9/3846

摘要： A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

摘要翻译： RISC（精简指令集）类型的高性能CPU采用标准化的固定指令大小，并且仅允许简化的存储器访问数据宽度和寻址模式。 指令集仅限于寄存器到寄存器操作和寄存器加载/存储操作。 包括允许使用先前建立的数据结构的字节操作指令包括进行寄存器中字节提取，插入和屏蔽以及非对齐加载和存储指令的功能。 提供加载/锁定和存储/条件指令允许实现原子字节写入。 通过提供条件移动指令，可以完全消除许多短分支。 条件移动指令测试寄存器，并且如果满足条件则将第二寄存器移动到第三寄存器; 该功能可以代替短分支，从而保持指令流的顺序性。

公开(公告)号：US5568624A

公开(公告)日：1996-10-22

申请号：US106316

申请日：1993-08-13

申请人： Richard L. Sites ,  Richard T. Witek

发明人： Richard L. Sites ,  Richard T. Witek

IPC分类号： G06F9/305 ,  G06F9/30 ,  G06F7/02 ,  G06F9/00

CPC分类号： G06F9/30032 ,  G06F9/30 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30072

摘要： A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

公开(公告)号：US5367705A

公开(公告)日：1994-11-22

申请号：US117482

申请日：1993-09-07

申请人： Richard L. Sites ,  Richard T. Witek

发明人： Richard L. Sites ,  Richard T. Witek

IPC分类号： G06F9/30 ,  G06F9/308 ,  G06F9/312 ,  G06F9/38 ,  G06F9/00 ,  G06F12/00

CPC分类号： G06F12/1027 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30054 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3816 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861 ,  G06F2212/652

摘要： A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing inregister byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes.

摘要翻译： RISC（精简指令集）类型的高性能CPU采用标准化的固定指令大小，并且仅允许简化的存储器访问数据宽度和寻址模式。 指令集仅限于寄存器到寄存器操作和寄存器加载/存储操作。 包括允许使用以前建立的数据结构的字节操作指令包括用于执行字节提取，插入和屏蔽以及非对齐加载和存储指令的功能。 提供加载/锁定和存储/条件指令允许实现原子字节写入。

公开(公告)号：US5430888A

公开(公告)日：1995-07-04

申请号：US143509

申请日：1993-10-26

申请人： Richard T. Witek ,  Douglas D. Williams ,  Timothy J. Stanley ,  David M. Fenwick ,  Douglas J. Burns ,  Rebecca L. Stamm ,  Richard Heye

发明人： Richard T. Witek ,  Douglas D. Williams ,  Timothy J. Stanley ,  David M. Fenwick ,  Douglas J. Burns ,  Rebecca L. Stamm ,  Richard Heye

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F15/78 ,  G06F17/16

CPC分类号： G06F15/8069 ,  G06F12/0859 ,  G06F15/8084 ,  G06F9/383

摘要： A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the requested for data. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.

摘要翻译： 用于将数据加载到寄存器和从寄存器存储数据的计算机处理器中的加载/存储管线具有用于存储数据的流水线内的高速缓冲存储器。 流水线包括支持多个未完成读请求未命中的缓冲区。 来自流水线的数据是独立于流水线的操作获取的，该数据对应于请求未命中。 然后可以用所请求的数据填充高速缓存存储器。 在流水线内提供高速缓冲存储器，以及用于支持高速缓冲存储器的缓冲器，加速计算机处理器的加载操作。

公开(公告)号：US5148544A

公开(公告)日：1992-09-15

申请号：US704710

申请日：1991-05-17

申请人： David N. Cutler ,  David A. Orbits ,  Dileep Bhandarkar ,  Wayne Cardoza ,  Richard T. Witek

发明人： David N. Cutler ,  David A. Orbits ,  Dileep Bhandarkar ,  Wayne Cardoza ,  Richard T. Witek

IPC分类号： G06F9/30 ,  G06F9/48

CPC分类号： G06F9/4812 ,  G06F9/30076

摘要： In a data procesing system having a kernel mode (i.e., for executing privileged instructions) and a user mode of operation, apparatus for responding to interrupt conditions includes a first register, subject to the control of the currently executing program for enabling the generation of a mode-related interrupt signal and includes a second register for indicating the presence of a pending mode-related interrupt condition and a third register for requesting a mode-related interrupt be entered in the second register. The mode of operation and the enable and pending interrupt condition registers are monitored and when the signals in the two registers have the appropriate relationship, an interrupt signal is generated to which a control program will respond. The contents of the first register can be controlled by the currently executing program which can control the enabling signal for the currently executing mode. The pending interrupt condition and the request registers may be accessed only from the privileged mode of operation.

摘要翻译： 在具有内核模式（即，用于执行特许指令）和用户操作模式的数据处理系统中，用于响应中断条件的装置包括第一寄存器，受到当前正在执行的程序的控制以使能生成 模式相关中断信号，并且包括用于指示存在待决模式相关中断条件的第二寄存器，并且用于请求模式相关中断的第三寄存器被输入到第二寄存器中。 监视操作模式和使能和待处理中断条件寄存器，并且当两个寄存器中的信号具有适当的关系时，产生一个控制程序将响应的中断信号。 第一寄存器的内容可以由当前执行的程序控制，该程序可以控制当前执行模式的使能信号。 挂起的中断条件和请求寄存器只能从特权操作模式访问。

公开(公告)号：US5148536A

公开(公告)日：1992-09-15

申请号：US224483

申请日：1988-07-25

申请人： Richard T. Witek ,  Douglas D. Williams ,  Timothy J. Stanley ,  David M. Fenwick ,  Douglas J. Burns ,  Rebecca L. Stamm ,  Richard Heye

发明人： Richard T. Witek ,  Douglas D. Williams ,  Timothy J. Stanley ,  David M. Fenwick ,  Douglas J. Burns ,  Rebecca L. Stamm ,  Richard Heye

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F15/78 ,  G06F17/16

CPC分类号： G06F15/8069 ,  G06F12/0859 ,  G06F15/8084 ,  G06F9/383

摘要： A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the data that has been requested. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.