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    Method of forming an FeRAM having a multi-layer hard mask and patterning thereof
    3.
    发明授权
    Method of forming an FeRAM having a multi-layer hard mask and patterning thereof 有权
    形成具有多层硬掩模并构图的FeRAM的方法

    公开(公告)号：US06828161B2

    公开(公告)日：2004-12-07

    申请号：US10313068

    申请日：2002-12-06

    申请人： Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Luigi Colombo ,  Theodore S. Moise, IV ,  J. Scott Martin

    发明人： Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Luigi Colombo ,  Theodore S. Moise, IV ,  J. Scott Martin

    IPC分类号： H01L2100

    CPC分类号： H01L27/11502 ,  H01L27/11507

    摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a multi-layer hard mask. The multi-layer hard mask comprises a hard masking layer overlying an etch stop layer. The etch stop layer is substantially more selective than the overlying masking layer with respect to an etch employed to remove the bottom electrode diffusion barrier layer. Therefore during an etch of the capacitor stack, an etch of the bottom electrode diffusion barrier layer results in a substantially complete removal of the hard masking layer. However, due to the substantial selectivity (e.g., 10:1 or more) of the etch stop layer with respect to the overlying masking layer, the etch stop layer completely protects the underlying top electrode, thereby preventing exposure thereof.

    摘要翻译： 本发明涉及一种形成FeRAM集成电路的方法，其包括形成多层硬掩模。 多层硬掩模包括覆盖在蚀刻停止层上的硬掩模层。 相对于用于去除底部电极扩散阻挡层的蚀刻，蚀刻停止层比上覆掩模层更具选择性。 因此，在电容器堆叠的蚀刻期间，底部电极扩散阻挡层的蚀刻导致硬掩模层的基本上完全去除。 然而，由于蚀刻停止层相对于上覆掩模层的实质选择性（例如10:1或更多），蚀刻停止层完全保护下面的顶部电极，从而防止其暴露。

    Method of forming an FeRAM capacitor having a bottom electrode diffusion barrier
    5.
    发明授权
    Method of forming an FeRAM capacitor having a bottom electrode diffusion barrier 有权
    形成具有底部电极扩散阻挡层的FeRAM电容器的方法

    公开(公告)号：US06773930B2

    公开(公告)日：2004-08-10

    申请号：US10305838

    申请日：2002-11-26

    申请人： Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Tomojuki Sakoda ,  Chiu Chi ,  Theodore S. Moise, IV

    发明人： Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Tomojuki Sakoda ,  Chiu Chi ,  Theodore S. Moise, IV

    IPC分类号： H01L2100

    CPC分类号： H01L27/11502 ,  H01L21/28568 ,  H01L27/11507 ,  H01L28/75

    摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a TiAlON bottom electrode diffusion barrier layer prior to formation of the bottom electrode layer in an FeRAM capacitor stack. Subsequently, when performing the capacitor stack etch, the portion of the TiAlON diffusion barrier layer not covered by the FeRAM capacitor stack is etched substantially anisotropically due to the oxygen within the TiAlON diffusion barrier layer substantially preventing a lateral etching thereof. In the above manner, an undercut of the TiAlON diffusion barrier layer under the FeRAM capacitor stack is prevented. In another aspect of the invention, a method of forming an FeRAM capacitor comprises forming a multi-layer bottom electrode diffusion barrier layer. Such formation comprises forming a TiN layer over the interlayer dielectric layer and the conductive contact and forming a diffusion barrier layer thereover. The TiN layer at least partially fills any seam that exists within the conductive contact, thus improving a conductivity between the FeRAM capacitor and a conductive contact in the interlayer dielectric.

    摘要翻译： 本发明涉及一种形成FeRAM集成电路的方法，其包括在FeRAM电容器堆叠中形成底部电极层之前形成TiAlON底部电极扩散阻挡层。 随后，当执行电容器堆叠蚀刻时，TiAlON扩散阻挡层中未被FeRAM电容器堆叠覆盖的部分被TiAlON扩散阻挡层内的氧基本上各向异性地蚀刻，基本上防止了其横向蚀刻。 以上述方式，防止了FeRAM电容器堆叠下的TiAlON扩散阻挡层的底切。 在本发明的另一方面，形成FeRAM电容器的方法包括形成多层底电极扩散阻挡层。 这种形成包括在层间电介质层和导电接触面上形成TiN层，并在其上形成扩散阻挡层。 TiN层至少部分地填充存在于导电接触中的任何接缝，从而提高了FeRAM电容器和层间电介质中的导电接触之间的导电性。

    Method of fabricating a ferroelectric memory cell
    8.
    发明授权
    Method of fabricating a ferroelectric memory cell 有权
    制造铁电存储单元的方法

    公开(公告)号：US06548343B1

    公开(公告)日：2003-04-15

    申请号：US09702985

    申请日：2000-10-31

    申请人： Scott R. Summerfelt ,  Theodore S. Moise ,  Guoqiang Xing ,  Luigi Colombo ,  Tomoyuki Sakoda ,  Stephen R. Gilbert ,  Alvin L. S. Loke ,  Shawming Ma ,  Rahim Kavari ,  Laura Wills-Mirkarimi ,  Jun Amano

    发明人： Scott R. Summerfelt ,  Theodore S. Moise ,  Guoqiang Xing ,  Luigi Colombo ,  Tomoyuki Sakoda ,  Stephen R. Gilbert ,  Alvin L. S. Loke ,  Shawming Ma ,  Rahim Kavari ,  Laura Wills-Mirkarimi ,  Jun Amano

    IPC分类号： H01L218242

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/57

    摘要： An embodiment of the instant invention is a method of fabricating a ferroelectric capacitor which is situated over a structure, the method comprising the steps of: forming a bottom electrode on the structure (124 of FIG. 1), the bottom electrode having a top surface and sides; forming a capacitor dielectric (126 of FIG. 1) comprised of a ferroelectric material on the bottom electrode, the capacitor dielectric having a top surface and sides; forming a top electrode (128 and 130 of FIG. 1) on the capacitor dielectric, the top electrode having a top surface and sides, the ferroelectric capacitor is comprised of the bottom electrode, the capacitor dielectric, and the top electrode; forming a barrier layer (118 and 120 of FIG. 1) on the side of the bottom electrode, the side of the capacitor dielectric, and the side of the top electrode; forming a dielectric layer on the barrier layer and the structure, the dielectric having a top surface and a bottom surface; and performing a thermal step for a duration at a temperature between 400 and 900 C. in an ambient comprised of a gas selected from the group consisting of: argon, nitrogen, and a combination thereof, the step of performing a thermal step being performed after the step of forming the barrier layer.

    摘要翻译： 本发明的一个实施例是制造位于结构上方的铁电电容器的方法，所述方法包括以下步骤：在所述结构（图1的124）上形成底电极，所述底电极具有顶表面 和边; 在底部电极上形成由铁电材料构成的电容器电介质（图1的126），电容器电介质具有顶表面和侧面; 在电容器电介质上形成顶电极（图1的128和130），顶电极具有顶表面和侧面，铁电电容器由底电极，电容器电介质和顶电极组成; 在底电极侧，电容器电介质侧和顶电极侧形成阻挡层（图1的118和120）; 在所述阻挡层和所述结构上形成电介质层，所述电介质具有顶表面和底表面; 并且在由选自氩，氮及其组合的气体组成的环境中在400-900℃的温度下进行热步骤，所述环境包括：在步骤 形成阻挡层的步骤。