利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

58 条记录 (耗时 0.054 秒)

    Method of forming an FeRAM having a multi-layer hard mask and patterning thereof
    3.
    发明授权
    Method of forming an FeRAM having a multi-layer hard mask and patterning thereof 有权
    形成具有多层硬掩模并构图的FeRAM的方法

    公开(公告)号：US06828161B2

    公开(公告)日：2004-12-07

    申请号：US10313068

    申请日：2002-12-06

    申请人： Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Luigi Colombo ,  Theodore S. Moise, IV ,  J. Scott Martin

    发明人： Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Luigi Colombo ,  Theodore S. Moise, IV ,  J. Scott Martin

    IPC分类号： H01L2100

    CPC分类号： H01L27/11502 ,  H01L27/11507

    摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a multi-layer hard mask. The multi-layer hard mask comprises a hard masking layer overlying an etch stop layer. The etch stop layer is substantially more selective than the overlying masking layer with respect to an etch employed to remove the bottom electrode diffusion barrier layer. Therefore during an etch of the capacitor stack, an etch of the bottom electrode diffusion barrier layer results in a substantially complete removal of the hard masking layer. However, due to the substantial selectivity (e.g., 10:1 or more) of the etch stop layer with respect to the overlying masking layer, the etch stop layer completely protects the underlying top electrode, thereby preventing exposure thereof.

    摘要翻译： 本发明涉及一种形成FeRAM集成电路的方法，其包括形成多层硬掩模。 多层硬掩模包括覆盖在蚀刻停止层上的硬掩模层。 相对于用于去除底部电极扩散阻挡层的蚀刻，蚀刻停止层比上覆掩模层更具选择性。 因此，在电容器堆叠的蚀刻期间，底部电极扩散阻挡层的蚀刻导致硬掩模层的基本上完全去除。 然而，由于蚀刻停止层相对于上覆掩模层的实质选择性（例如10:1或更多），蚀刻停止层完全保护下面的顶部电极，从而防止其暴露。

    Method of forming an FeRAM capacitor having a bottom electrode diffusion barrier
    5.
    发明授权
    Method of forming an FeRAM capacitor having a bottom electrode diffusion barrier 有权
    形成具有底部电极扩散阻挡层的FeRAM电容器的方法

    公开(公告)号：US06773930B2

    公开(公告)日：2004-08-10

    申请号：US10305838

    申请日：2002-11-26

    申请人： Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Tomojuki Sakoda ,  Chiu Chi ,  Theodore S. Moise, IV

    发明人： Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Tomojuki Sakoda ,  Chiu Chi ,  Theodore S. Moise, IV

    IPC分类号： H01L2100

    CPC分类号： H01L27/11502 ,  H01L21/28568 ,  H01L27/11507 ,  H01L28/75

    摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a TiAlON bottom electrode diffusion barrier layer prior to formation of the bottom electrode layer in an FeRAM capacitor stack. Subsequently, when performing the capacitor stack etch, the portion of the TiAlON diffusion barrier layer not covered by the FeRAM capacitor stack is etched substantially anisotropically due to the oxygen within the TiAlON diffusion barrier layer substantially preventing a lateral etching thereof. In the above manner, an undercut of the TiAlON diffusion barrier layer under the FeRAM capacitor stack is prevented. In another aspect of the invention, a method of forming an FeRAM capacitor comprises forming a multi-layer bottom electrode diffusion barrier layer. Such formation comprises forming a TiN layer over the interlayer dielectric layer and the conductive contact and forming a diffusion barrier layer thereover. The TiN layer at least partially fills any seam that exists within the conductive contact, thus improving a conductivity between the FeRAM capacitor and a conductive contact in the interlayer dielectric.

    摘要翻译： 本发明涉及一种形成FeRAM集成电路的方法，其包括在FeRAM电容器堆叠中形成底部电极层之前形成TiAlON底部电极扩散阻挡层。 随后，当执行电容器堆叠蚀刻时，TiAlON扩散阻挡层中未被FeRAM电容器堆叠覆盖的部分被TiAlON扩散阻挡层内的氧基本上各向异性地蚀刻，基本上防止了其横向蚀刻。 以上述方式，防止了FeRAM电容器堆叠下的TiAlON扩散阻挡层的底切。 在本发明的另一方面，形成FeRAM电容器的方法包括形成多层底电极扩散阻挡层。 这种形成包括在层间电介质层和导电接触面上形成TiN层，并在其上形成扩散阻挡层。 TiN层至少部分地填充存在于导电接触中的任何接缝，从而提高了FeRAM电容器和层间电介质中的导电接触之间的导电性。

    One step deposition process for the top electrode and hardmask in a ferroelectric memory cell
    8.
    发明授权
    One step deposition process for the top electrode and hardmask in a ferroelectric memory cell 有权
    在铁电存储器单元中的顶部电极和硬掩模的一步沉积工艺

    公开(公告)号：US06576482B1

    公开(公告)日：2003-06-10

    申请号：US10140481

    申请日：2002-05-07

    申请人： Sanjeev Aggarwal ,  Scott R. Summerfelt ,  Stevan G. Hunter

    发明人： Sanjeev Aggarwal ,  Scott R. Summerfelt ,  Stevan G. Hunter

    IPC分类号： H01L2100

    CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L21/3143 ,  H01L28/55

    摘要： One aspect of the invention relates to a one-step process for forming a transition metal aluminum oxynitride layer over a transition metal aluminum nitride layer. The transition metal aluminum nitride layer is sputter deposited using a transition metal/aluminum target in an atmosphere containing nitrogen. Subsequently, the oxygen content of the atmosphere is increased, whereby the transition metal aluminum oxynitride layer can be deposited without interrupting the process or otherwise reconditioning the target. Another aspect of the invention relates to depositing a transition metal aluminum nitride layer over a transition metal aluminum oxynitride layer by reducing the oxygen content of the atmosphere. The invention provides a one-step process for depositing a hard mask layer and upper diffusion barrier layer for the capacitor stack of a FeRAM. A top electrode, such as an Ir/IrO electrode, can be deposited as part of the one-step process.

    摘要翻译： 本发明的一个方面涉及在过渡金属氮化铝层上形成过渡金属铝氧氮化物层的一步法。 使用过渡金属/铝靶在含氮的气氛中溅射沉积过渡金属氮化铝层。 随后，气氛的氧含量增加，从而可以沉积过渡金属铝氮氧化物层，而不会中断该工艺或以其他方式修复靶。 本发明的另一方面涉及通过降低大气中的氧含量在过渡金属铝氮氧化物层上沉积过渡金属氮化铝层。 本发明提供了一种用于沉积FeRAM的电容器堆叠的硬掩模层和上扩散阻挡层的一步法。 作为一步法的一部分，可以沉积上电极，例如Ir / IrO电极。