Plasma etching apparatus having a sealing member coupling an upper
electrode to an etching chamber
    1.
    发明授权
    Plasma etching apparatus having a sealing member coupling an upper electrode to an etching chamber 有权
    等离子体蚀刻装置具有将上部电极耦合到蚀刻室的密封构件

    公开(公告)号:US6074519A

    公开(公告)日:2000-06-13

    申请号:US389432

    申请日:1999-09-03

    CPC分类号: H01J37/32458

    摘要: A plasma etching apparatus is provided having a sealing member coupling an upper electrode to the plasma etching chamber. A peripheral portion of the inner surface of the upper electrode includes a planar surface across both anodized and non-anodized portions of the surface in the peripheral contact region adjacent to the upper portion of the sidewalls of the chamber assembly. A sealing member is positioned between the planar, peripheral portion of the second electrode and the upper portion of the sidewalls to provide a seal therebetween. The anodized portion of the inner surface of the upper electrode may extend over the area adjacent to the opening in the chamber housing and further extend into the peripheral portion beyond the sealing member to reduce the potential for arcing to occur to the non-anodized section during plasma etching operations. Plasma etching apparatus according to the present invention may provide improved sealing, thereby allowing improved control of vacuum level and concentration of processing gas within the plasma etching chamber during etching operations.

    摘要翻译: 提供一种等离子体蚀刻装置,其具有将上部电极耦合到等离子体蚀刻室的密封构件。 上电极的内表面的周边部分包括在与腔室组件的侧壁的上部相邻的周边接触区域中的表面的阳极氧化和非阳极氧化部分的平面。 密封构件位于第二电极的平面周边部分和侧壁的上部之间,以在它们之间提供密封。 上电极的内表面的阳极氧化部分可以在邻近腔室壳体中的开口的区域上延伸,并且进一步延伸到超过密封构件的周边部分中,以减少非阳极氧化部分发生电弧的可能性 等离子体蚀刻操作。 根据本发明的等离子体蚀刻装置可以提供改进的密封,从而允许在蚀刻操作期间改进等离子体蚀刻室内的处理气体的真空度和浓度的控制。

    Methods of forming dual damascene structures
    2.
    发明授权
    Methods of forming dual damascene structures 失效
    形成双镶嵌结构的方法

    公开(公告)号:US08372198B2

    公开(公告)日:2013-02-12

    申请号:US12043576

    申请日:2008-03-06

    IPC分类号: C30B21/02

    摘要: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.

    摘要翻译: 公开了一种双镶嵌结构和形成双镶嵌结构的方法。 双镶嵌结构包括绝缘构件,单晶构件和填充构件。 绝缘构件具有双镶嵌形状的开口。 填充构件形成在开口的侧面上。 单晶构件接触填充构件。 单晶构件填充开口。 为了形成双镶嵌结构,形成具有部分填充有初级单晶构件的开口的绝缘构件。 填充构件形成在开口的侧面上。 外延的初步单晶构件生长以填满开口。 由于填充构件位于单晶构件和绝缘构件之间,所以在单晶构件和绝缘构件之间可能会减小空隙形成。

    Dual damascene structure and methods of forming the same
    3.
    发明授权
    Dual damascene structure and methods of forming the same 失效
    双镶嵌结构及其形成方法

    公开(公告)号:US07358126B2

    公开(公告)日:2008-04-15

    申请号:US11333110

    申请日:2006-01-17

    IPC分类号: H01L23/43 H01L21/4763

    摘要: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.

    摘要翻译: 公开了一种双镶嵌结构和形成双镶嵌结构的方法。 双镶嵌结构包括绝缘构件,单晶构件和填充构件。 绝缘构件具有双镶嵌形状的开口。 填充构件形成在开口的侧面上。 单晶构件接触填充构件。 单晶构件填充开口。 为了形成双镶嵌结构,形成具有部分填充有初级单晶构件的开口的绝缘构件。 填充构件形成在开口的侧面上。 外延的初步单晶构件生长以填满开口。 由于填充构件位于单晶构件和绝缘构件之间,所以在单晶构件和绝缘构件之间可能会减小空隙形成。

    Methods of manufacturing a semiconductor device using a layer suspended across a trench
    4.
    发明授权
    Methods of manufacturing a semiconductor device using a layer suspended across a trench 有权
    使用悬挂在沟槽上的层的半导体器件的制造方法

    公开(公告)号:US08003487B2

    公开(公告)日:2011-08-23

    申请号:US12335831

    申请日:2008-12-16

    IPC分类号: H01L21/76

    CPC分类号: H01L21/76229 H01L21/76232

    摘要: In methods of forming a trench, first patterns separated from each other by a first width and second patterns separated from each other by a second width are formed on a substrate. The second width is wider than the first width. The substrate is etched using the first patterns and the second patterns to form a first trench having a first depth and a preliminary second trench having a second depth. A sacrificial layer is formed to fill up a space between the first patterns. The substrate is etched using the sacrificial layer to form a second trench having a third depth deeper than the second depth.

    摘要翻译: 在形成沟槽的方法中,在衬底上形成以彼此分开第二宽度的第一宽度和第二图案彼此分开的第一图案。 第二宽度比第一宽度宽。 使用第一图案和第二图案蚀刻衬底,以形成具有第一深度的第一沟槽和具有第二深度的初步第二沟槽。 形成牺牲层以填充第一图案之间的空间。 使用牺牲层蚀刻衬底以形成具有比第二深度更深的第三深度的第二沟槽。

    Method of manufacturing integrated circuit device including recessed channel transistor
    5.
    发明授权
    Method of manufacturing integrated circuit device including recessed channel transistor 失效
    集成电路器件制造方法,包括凹陷沟道晶体管

    公开(公告)号:US07326619B2

    公开(公告)日:2008-02-05

    申请号:US10902642

    申请日:2004-07-28

    IPC分类号: H01L21/31 H01L21/336

    摘要: A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.

    摘要翻译: 根据本发明的一些实施例的方法包括通过在集成衬底上形成沟槽器件隔离区域来限定有源区域,形成掩模图案,其暴露有源区域的沟道子区域和与该区域相邻的沟槽器件隔离区域 使用掩模图案作为蚀刻掩模蚀刻由掩模图案曝光的沟槽器件隔离区域,以凹陷到第一深度,蚀刻沟道子区域以形成栅极沟槽,栅极沟道具有第二 深度比使用掩模图案的第一深度深的蚀刻掩模,以及形成填充栅极沟槽的凹槽。

    Dual damascene structure and methods of forming the same
    6.
    发明申请
    Dual damascene structure and methods of forming the same 失效
    双镶嵌结构及其形成方法

    公开(公告)号:US20060163738A1

    公开(公告)日:2006-07-27

    申请号:US11333110

    申请日:2006-01-17

    IPC分类号: H01L23/48

    摘要: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.

    摘要翻译: 公开了一种双镶嵌结构和形成双镶嵌结构的方法。 双镶嵌结构包括绝缘构件,单晶构件和填充构件。 绝缘构件具有双镶嵌形状的开口。 填充构件形成在开口的侧面上。 单晶构件接触填充构件。 单晶构件填充开口。 为了形成双镶嵌结构,形成具有部分填充有初级单晶构件的开口的绝缘构件。 填充构件形成在开口的侧面上。 外延的初步单晶构件生长以填满开口。 由于填充构件位于单晶构件和绝缘构件之间,所以在单晶构件和绝缘构件之间可能会减小空隙形成。

    Methods of fabricating semiconductor device including fin-fet
    7.
    发明授权
    Methods of fabricating semiconductor device including fin-fet 失效
    制造半导体器件的方法包括鳍片

    公开(公告)号:US07745290B2

    公开(公告)日:2010-06-29

    申请号:US11773372

    申请日:2007-07-03

    IPC分类号: H01L21/336

    CPC分类号: H01L29/66795 H01L29/7851

    摘要: A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.

    摘要翻译: 一种制造包括鳍状场效应晶体管(Fin-FET)的半导体器件的方法包括:在半导体衬底上形成牺牲棒,对牺牲棒进行构图以在半导体衬底上形成牺牲岛,形成器件隔离层以填充第 牺牲岛,选择性地去除牺牲岛以将牺牲岛下方的半导体衬底暴露出来,并且使用器件隔离层作为蚀刻掩模来各向异性蚀刻暴露的半导体衬底以形成凹陷沟道区。 凹陷沟道区域允许晶体管的沟道宽度和沟道长度增加,从而减少在高度集成的半导体器件中的短沟道效应和窄沟道效应的发生。

    Methods of Forming Dual Damascene Structures
    8.
    发明申请
    Methods of Forming Dual Damascene Structures 失效
    形成双镶嵌结构的方法

    公开(公告)号:US20080149021A1

    公开(公告)日:2008-06-26

    申请号:US12043576

    申请日:2008-03-06

    IPC分类号: C30B25/02

    摘要: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.

    摘要翻译: 公开了一种双镶嵌结构和形成双镶嵌结构的方法。 双镶嵌结构包括绝缘构件,单晶构件和填充构件。 绝缘构件具有双镶嵌形状的开口。 填充构件形成在开口的侧面上。 单晶构件接触填充构件。 单晶构件填充开口。 为了形成双镶嵌结构,形成具有部分填充有初级单晶构件的开口的绝缘构件。 填充构件形成在开口的侧面上。 外延的初步单晶构件生长以填满开口。 由于填充构件位于单晶构件和绝缘构件之间,所以在单晶构件和绝缘构件之间可能会减小空隙形成。

    MOS transistor with recessed gate and method of fabricating the same
    9.
    发明授权
    MOS transistor with recessed gate and method of fabricating the same 失效
    具有凹陷栅极的MOS晶体管及其制造方法

    公开(公告)号:US07157770B2

    公开(公告)日:2007-01-02

    申请号:US10884223

    申请日:2004-07-01

    IPC分类号: H01L29/76

    摘要: A MOS transistor with a recessed gate and a method of fabricating the same: The MOS transistor comprises a semiconductor substrate, and a trench isolation layer located in a predetermined region of the semiconductor substrate for defining an active region. The trench isolation layer has a negative slope on at least a lower sidewall thereof. A recessed gate is located in a predetermined region of the active region, and a bottom surface of the recessed gate is placed adjacent the negatively slopped sidewall of the trench isolation layer.

    摘要翻译: 具有凹陷栅极的MOS晶体管及其制造方法:MOS晶体管包括半导体衬底和位于半导体衬底的用于限定有源区的预定区域中的沟槽隔离层。 沟槽隔离层在至少其下侧壁上具有负斜率。 凹入栅极位于有源区的预定区域中,并且凹入栅极的底表面邻近沟槽隔离层的负斜面侧壁放置。

    Method of manufacturing integrated circuit device including recessed channel transistor
    10.
    发明申请
    Method of manufacturing integrated circuit device including recessed channel transistor 失效
    集成电路器件制造方法,包括凹陷沟道晶体管

    公开(公告)号:US20050042833A1

    公开(公告)日:2005-02-24

    申请号:US10902642

    申请日:2004-07-28

    摘要: A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.

    摘要翻译: 根据本发明的一些实施例的方法包括通过在集成衬底上形成沟槽器件隔离区域来限定有源区域,形成掩模图案,其暴露有源区域的沟道子区域和与该区域相邻的沟槽器件隔离区域 使用掩模图案作为蚀刻掩模蚀刻由掩模图案曝光的沟槽器件隔离区域,以凹陷到第一深度,蚀刻沟道子区域以形成栅极沟槽,栅极沟道具有第二 深度比使用掩模图案的第一深度深的蚀刻掩模,以及形成填充栅极沟槽的凹槽。