-
公开(公告)号：US08001411B2
公开(公告)日：2011-08-16
申请号：US11859819
申请日：2007-09-24
申请人： Sean Michael Carey , William Vincent Huott , Christian Jacobi , Guenter Mayer , Timothy Gerard McNamara , Chung-Lung Kevin Shum , Hans-Werner Tast , Michael Hemsley Wood
发明人： Sean Michael Carey , William Vincent Huott , Christian Jacobi , Guenter Mayer , Timothy Gerard McNamara , Chung-Lung Kevin Shum , Hans-Werner Tast , Michael Hemsley Wood
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , G06F1/3275 , G11C7/22 , G11C7/222 , G11C11/413 , Y02D10/14
摘要： A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times itscommencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.
摘要翻译： 一种用于在操作中产生本地时钟域的方法包括以下步骤：在操作期间接收用于逻辑的较慢部分的时钟频率测量; 产生本地信号以指示操作的开始并用作时钟选通信号; 将时钟门控信号锁存到选定的周期; 基于时钟选通信号产生时钟域控制，使得操作在所选择的周期上重新启动; 并且在未锁定的锁存器中传播时钟门控信号多个周期，使得第二操作被限制为被启动直到操作完成。
-
公开(公告)号：US20090083569A1
公开(公告)日：2009-03-26
申请号：US11859819
申请日：2007-09-24
申请人： Sean Michael Carey , William Vincent Huott , Christian Jacobi , Guenter Mayer , Timothy Gerard McNamara , Chung-Lung Kevin Shum , Hans-Werner Tast , Michael Hemsley Wood
发明人： Sean Michael Carey , William Vincent Huott , Christian Jacobi , Guenter Mayer , Timothy Gerard McNamara , Chung-Lung Kevin Shum , Hans-Werner Tast , Michael Hemsley Wood
CPC分类号： G06F1/04 , G06F1/3275 , G11C7/22 , G11C7/222 , G11C11/413 , Y02D10/14
摘要： A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times its commencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.
摘要翻译： 一种用于在操作中产生本地时钟域的方法包括以下步骤：在操作期间接收用于逻辑的较慢部分的时钟频率测量; 产生本地信号以指示操作的开始并用作时钟选通信号; 将时钟门控信号锁存到选定的周期; 基于时钟门控信号产生时钟域控制，使得操作在所选择的周期上开始生效; 并且在未锁定的锁存器中传播时钟门控信号多个周期，使得第二操作被限制为被启动直到操作完成。
-
3.发明授权Method, system, and computer program product for handling errors in a cache without processor core recovery 有权用于在没有处理器核心恢复的情况下处理高速缓存中的错误的方法，系统和计算机程序产品公开(公告)号：US07987384B2
公开(公告)日：2011-07-26
申请号：US12029516
申请日：2008-02-12
IPC分类号： G06F11/00
CPC分类号： G06F12/0804 , G06F11/1064 , G06F12/0855 , G06F12/0897
摘要： A method for handling errors in a cache memory without processor core recovery includes receiving a fetch request for data from a processor and simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor. The fetched data is received from a higher-level cache into a low level cache of the processor. Upon determining that the fetched data failed an error check indicating that the fetched data is corrupted, the method includes requesting an execution pipeline to discontinue processing and flush its contents, and initiating a clean up sequence, which includes sending an invalidation request to the low level cache causing the low level cache to remove lines associated with the corrupted data, and requesting the execution pipeline to restart. The execution pipeline accesses a copy of the requested data from a higher-level storage location.
摘要翻译： 用于处理高速缓冲存储器中没有处理器核心恢复的错误的方法包括从处理器接收对数据的取出请求，同时发送取出的数据以及将获取的数据的奇偶校验与校验符相匹配的处理器。 将获取的数据从较高级别的高速缓存接收到处理器的低级缓存中。 在确定所获取的数据失败的情况下，指示所取出的数据被破坏的错误检查失败，所述方法包括请求执行流水线中断处理和刷新其内容，以及启动清理序列，其包括将无效请求发送到低级别 缓存导致低级缓存删除与损坏的数据相关联的行，并请求执行管道重新启动。 执行流水线从较高级别的存储位置访问所请求的数据的副本。
-
4.发明申请METHOD AND SYSTEM FOR A MULTI-LEVEL VIRTUAL/REAL CACHE SYSTEM WITH SYNONYM RESOLUTION 有权具有同步分辨率的多级虚拟/实时缓存系统的方法和系统公开(公告)号：US20090216949A1
公开(公告)日：2009-08-27
申请号：US12036357
申请日：2008-02-25
申请人： Barry W. Krumm , Christian Jacobi , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai , Ching-Farn E. Wu
发明人： Barry W. Krumm , Christian Jacobi , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai , Ching-Farn E. Wu
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0817
摘要： Method and system for a multi-level virtual/real cache system with synonym resolution. An exemplary embodiment includes a multi-level cache hierarchy, including a set of L1 caches associated with one or more processor cores and a set of L2 caches, wherein the set of L1 caches are a subset of the set of L2 caches, wherein the set of L1 caches underneath a given L2 cache are associated with one or more of the processor cores.
摘要翻译： 具有同义词解析的多级虚拟/真实缓存系统的方法和系统。 一个示例性实施例包括多级高速缓存层级，其包括与一个或多个处理器核心和一组L2高速缓存相关联的一组L1高速缓存，其中所述一组L1高速缓存是所述一组L2高速缓存的子集，其中所述集合 在一个给定的L2高速缓存下面的L1高速缓存与一个或多个处理器核心相关联。
-
5.发明授权Method and system for a multi-level virtual/real cache system with synonym resolution 有权具有同义词解析的多级虚拟/真实缓存系统的方法和系统公开(公告)号：US08041894B2
公开(公告)日：2011-10-18
申请号：US12036357
申请日：2008-02-25
申请人： Barry W. Krumm , Christian Jacobi , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai , Ching-Farn E. Wu
发明人： Barry W. Krumm , Christian Jacobi , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai , Ching-Farn E. Wu
IPC分类号： G06F13/00
CPC分类号： G06F12/0811 , G06F12/0817
摘要： Method and system for a multi-level virtual/real cache system with synonym resolution. An exemplary embodiment includes a multi-level cache hierarchy, including a set of L1 caches associated with one or more processor cores and a set of L2 caches, wherein the set of L1 caches are a subset of the set of L2 caches, wherein the set of L1 caches underneath a given L2 cache are associated with one or more of the processor cores.
摘要翻译： 具有同义词解析的多级虚拟/真实缓存系统的方法和系统。 一个示例性实施例包括多级高速缓存层级，其包括与一个或多个处理器核心和一组L2高速缓存相关联的一组L1高速缓存，其中所述一组L1高速缓存是所述一组L2高速缓存的子集，其中所述集合 在一个给定的L2高速缓存下面的L1高速缓存与一个或多个处理器核心相关联。
-
6.发明申请METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR HANDLING ERRORS IN A CACHE WITHOUT PROCESSOR CORE RECOVERY 有权方法，系统和计算机程序产品，用于处理高速缓存中的错误，无需处理器核心恢复公开(公告)号：US20090204766A1
公开(公告)日：2009-08-13
申请号：US12029516
申请日：2008-02-12
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F11/1064 , G06F12/0855 , G06F12/0897
摘要： A method for handling errors in a cache memory without processor core recovery includes receiving a fetch request for data from a processor and simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor. The fetched data is received from a higher-level cache into a low level cache of the processor. Upon determining that the fetched data failed an error check indicating that the fetched data is corrupted, the method includes requesting an execution pipeline to discontinue processing and flush its contents, and initiating a clean up sequence, which includes sending an invalidation request to the low level cache causing the low level cache to remove lines associated with the corrupted data, and requesting the execution pipeline to restart. The execution pipeline accesses a copy of the requested data from a higher-level storage location.
摘要翻译： 用于处理高速缓冲存储器中没有处理器核心恢复的错误的方法包括从处理器接收对数据的取出请求，同时发送取出的数据以及将获取的数据的奇偶校验与校验符相匹配的处理器。 将获取的数据从较高级别的高速缓存接收到处理器的低级缓存中。 在确定所获取的数据失败的情况下，指示所取出的数据被破坏的错误检查失败，所述方法包括请求执行流水线中断处理和刷新其内容，以及启动清理序列，其包括将无效请求发送到低级别 缓存导致低级缓存删除与损坏的数据相关联的行，并请求执行管道重新启动。 执行流水线从较高级别的存储位置访问所请求的数据的副本。
-
公开(公告)号：US20130339615A1
公开(公告)日：2013-12-19
申请号：US13524386
申请日：2012-06-15
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F9/467 , G06F11/1474 , G06F12/0828
摘要： Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The one or more store instructions are initiated within an active transaction and include store data. The active transaction effectively delays committing stores to memory until successful completion of the active transaction. The store data is stored in a local storage buffer causing alterations to the local storage buffer from a first state to a second state. A signal is received that the active transaction has terminated. If the active transaction has terminated abnormally then: the local storage buffer is reverted back to the first state if the store data was stored by a transactional store instruction, and is propagated to a shared cache if the store instruction is non-transactional.
摘要翻译： 实施例涉及控制事务和非交易存储的可观察性。 一方面包括接收一个或多个存储指令。 一个或多个存储指令在活动事务中启动并且包括存储数据。 活动事务有效地延迟将存储提交到存储器，直到成功完成活动事务。 存储数据存储在本地存储缓冲器中，导致本地存储缓冲器从第一状态到第二状态的改变。 接收到有效事务终止的信号。 如果活动事务已经异常终止，则：如果存储数据由事务存储指令存储，则本地存储缓冲区被恢复到第一状态，并且如果存储指令是非事务性的则将其传播到共享高速缓存。
-
8.发明申请METHOD TO VERIFY AN IMPLEMENTED COHERENCY ALGORITHM OF A MULTI PROCESSOR ENVIRONMENT 失效验证多处理器环境的实现的相似算法的方法公开(公告)号：US20100146210A1
公开(公告)日：2010-06-10
申请号：US12328242
申请日：2008-12-04
CPC分类号： G06F12/0815
摘要： A method to verify an implemented coherency algorithm of a multi processor environment on a single processor model is described, comprising the steps of: generating a reference model reflecting a private cache hierarchy of a single processor within a multi processor environment, stimulating the private cache hierarchy with simulated requests and/or cross invalidations from a core side and/or from a nest side, augmenting all data available in the private cache hierarchy with two construction dates and two expiration dates, set based on interface events, wherein multi processor coherency is not observed if the cache hierarchy ever returns data to the processor with an expiration date that is older than the latest construction date of all data used before. Further a single processor model and a computer program product to execute said method are described.
摘要翻译： 描述了在单个处理器模型上验证多处理器环境的实现的一致性算法的方法，包括以下步骤：生成反映多处理器环境内的单个处理器的专用高速缓存层级的参考模型，以刺激专用高速缓存层级 具有来自核心侧和/或来自嵌套侧的模拟请求和/或交叉无效，基于接口事件设置两个构建日期和两个到期日期，扩充专用高速缓存层级中可用的所有数据，其中多处理器一致性不是 观察缓存层次结构是否已将数据返回给处理器，其过期日期早于之前使用的所有数据的最新构建日期。 此外，描述了执行所述方法的单个处理器模型和计算机程序产品。
-
公开(公告)号：US09298631B2
公开(公告)日：2016-03-29
申请号：US13524386
申请日：2012-06-15
CPC分类号： G06F12/084 , G06F9/467 , G06F11/1474 , G06F12/0828
摘要： Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The one or more store instructions are initiated within an active transaction and include store data. The active transaction effectively delays committing stores to memory until successful completion of the active transaction. The store data is stored in a local storage buffer causing alterations to the local storage buffer from a first state to a second state. A signal is received that the active transaction has terminated. If the active transaction has terminated abnormally then: the local storage buffer is reverted back to the first state if the store data was stored by a transactional store instruction, and is propagated to a shared cache if the store instruction is non-transactional.
-
公开(公告)号：US20120059996A1
公开(公告)日：2012-03-08
申请号：US12876366
申请日：2010-09-07
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0811
摘要： A mechanism is provided for avoiding cross-interrogates for a streaming data optimized level one cache. The mechanism adds a set of dedicated registers, referred to as “copex registers,” to track ownership of the cache lines that the co-processor's L1 cache holds exclusive. The mechanism extends the cache directory of the L2 cache by a bit that identifies exclusive ownership of a cache line in the co-processor cache. The co-processor continuously provides an indication of which copex registers are valid. On any action that requires a directory lookup in the L2 cache, the mechanism compares the valid copex registers against the lookup address in parallel to the directory lookup. The mechanism considers the “exclusive ownership in co-processor” bit in the directory valid only if the cache line is also currently in a valid copex register.
摘要翻译： 提供了一种用于避免流数据优化的一级缓存的交叉询问的机制。 该机制添加了一组专用寄存器（称为“copex寄存器”）来跟踪协处理器的L1高速缓存保存的高速缓存行的所有权。 该机制将L2高速缓存的缓存目录扩展一个位，以识别协处理器高速缓存中高速缓存行的独占所有权。 协处理器连续提供哪些共享寄存器有效的指示。 对于需要在L2缓存中进行目录查找的任何操作，该机制将将有效的copex寄存器与查找地址并行地与目录查找进行比较。 该机制认为目录中的“独占所有权协同处理器”位只有当高速缓存行当前还在有效的copex寄存器中时才有效。
-
-
-
-
-
-
-
-
-
搜索结果
47 条记录 (耗时 0.038 秒)
