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公开(公告)号：US07939416B2
公开(公告)日：2011-05-10
申请号：US12935924
申请日：2009-03-30
IPC分类号： H01L21/8222
CPC分类号： H01L29/66242 , H01L21/8249 , H01L29/0634 , H01L29/0692 , H01L29/66287 , H01L29/66795 , H01L29/732 , H01L29/7371
摘要： A method of manufacturing a bipolar transistor is compatible with FinFET processing. A collector region (18) is formed and patterned, base contact regions (26) formed on either side, and a gap formed between the base contact region. A base (28), spacers (30) and an emitter (32) are formed in the gap.
摘要翻译： 制造双极晶体管的方法与FinFET处理兼容。 形成集电极区域（18）并构图，形成在两侧的基极接触区域（26）和形成在基极接触区域之间的间隙。 在间隙中形成基座（28），间隔件（30）和发射极（32）。
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公开(公告)号：US20110034001A1
公开(公告)日：2011-02-10
申请号：US12935924
申请日：2009-03-30
IPC分类号： H01L21/8222
CPC分类号： H01L29/66242 , H01L21/8249 , H01L29/0634 , H01L29/0692 , H01L29/66287 , H01L29/66795 , H01L29/732 , H01L29/7371
摘要： A method of manufacturing a bipolar transistor is compatible with FinFET processing. A collector region (18) is formed and patterned, base contact regions (26) formed on either side, and a gap formed between the base contact region. A base (28), spacers (30) and an emitter (32) are formed in the gap.
摘要翻译： 制造双极晶体管的方法与FinFET处理兼容。 形成集电极区域（18）并构图，形成在两侧的基极接触区域（26）和形成在基极接触区域之间的间隙。 在间隙中形成基座（28），间隔件（30）和发射极（32）。
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公开(公告)号：US20100022056A1
公开(公告)日：2010-01-28
申请号：US12439363
申请日：2007-08-29
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L29/407 , H01L29/66242
摘要： The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate (17) in a trench (7) adjacent to a collector region (21), which field plate (17) employs a reduced surface field (Resurf) effect. The Resurf effect reshapes the electric field distribution in the collector region (21) such that for the same collector-base breakdown voltage the doping concentration of the collector region (21) can effectively be increased resulting in a reduced collector resistance and hence an increased bipolar transistor speed. The method comprises a step of forming a base window (6) in a first base layer (4) thereby exposing a top surface of the collector region (21) and a part of an isolation region (3). The trench (7) is formed by removing the exposed part of the isolation region (3), after which isolation layers (9,10) are formed on the surface of the trench (7). A second base layer (13) is formed on the isolation layer (10), thereby forming the field plate (17), on the top surface of the collector region (21), thereby forming a base region (31), and on a sidewall of the first base layer (4), thereby forming an electrical connection between the first base layer (4), the base region (31) and the field plate (17). An emitter region (41) is formed on a top part of the base region (31), thereby forming the Resurf bipolar transistor.
摘要翻译： 本发明提供了制造双极晶体管的替代和较不复杂的方法，其包括在与集电极区域（21）相邻的沟槽（7）中的场板（17），该场板（17）采用减小的表面场（Resurf ）效果。 Resurf效应重塑了集电极区域（21）中的电场分布，使得对于相同的集电极 - 基极击穿电压，可以有效地增加集电极区域（21）的掺杂浓度，从而降低集电极电阻，从而增加双极性 晶体管速度。 该方法包括在第一基层（4）中形成基窗（6）从而暴露集电区（21）的顶表面和隔离区（3）的一部分的步骤。 通过去除隔离区域（3）的露出部分形成沟槽（7），之后隔离层（9,10）形成在沟槽（7）的表面上。 在隔离层（10）上形成第二基层（13），从而在集电区域（21）的顶面上形成场板（17），从而形成基极区域（31） 从而在第一基底层（4），基底区域（31）和场板（17）之间形成电连接。 在基极区域（31）的顶部形成发射极区域（41），从而形成Resurf双极型晶体管。
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公开(公告)号：US08026146B2
公开(公告)日：2011-09-27
申请号：US12439363
申请日：2007-08-29
IPC分类号： H01L21/8222
CPC分类号： H01L29/7378 , H01L29/407 , H01L29/66242
摘要： The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate (17) in a trench (7) adjacent to a collector region (21), which field plate (17) employs a reduced surface field (Resurf) effect. The Resurf effect reshapes the electric field distribution in the collector region (21) such that for the same collector-base breakdown voltage the doping concentration of the collector region (21) can effectively be increased resulting in a reduced collector resistance and hence an increased bipolar transistor speed. The method comprises a step of forming a base window (6) in a first base layer (4) thereby exposing a top surface of the collector region (21) and a part of an isolation region (3). The trench (7) is formed by removing the exposed part of the isolation region (3), after which isolation layers (9,10) are formed on the surface of the trench (7). A second base layer (13) is formed on the isolation layer (10), thereby forming the field plate (17), on the top surface of the collector region (21), thereby forming a base region (31), and on a sidewall of the first base layer (4), thereby forming an electrical connection between the first base layer (4), the base region (31) and the field plate (17). An emitter region (41) is formed on a top part of the base region (31), thereby forming the Resurf bipolar transistor.
摘要翻译： 本发明提供了制造双极晶体管的替代和较不复杂的方法，其包括在与集电极区域（21）相邻的沟槽（7）中的场板（17），该场板（17）采用减小的表面场（Resurf ）效果。 Resurf效应重塑了集电极区域（21）中的电场分布，使得对于相同的集电极 - 基极击穿电压，可以有效地增加集电极区域（21）的掺杂浓度，从而降低集电极电阻，从而增加双极性 晶体管速度。 该方法包括在第一基层（4）中形成基窗（6）从而暴露集电区（21）的顶表面和隔离区（3）的一部分的步骤。 通过去除隔离区域（3）的露出部分形成沟槽（7），之后隔离层（9,10）形成在沟槽（7）的表面上。 在隔离层（10）上形成第二基层（13），从而在集电区域（21）的顶面上形成场板（17），从而形成基极区域（31） 从而在第一基底层（4），基底区域（31）和场板（17）之间形成电连接。 在基极区域（31）的顶部形成发射极区域（41），从而形成Resurf双极型晶体管。
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5.发明授权Method of manufacturing a bipolar transistor semiconductor device and semiconductor devices obtained thereby 有权制造双极晶体管半导体器件的方法和由此获得的半导体器件公开(公告)号：US08431966B2
公开(公告)日：2013-04-30
申请号：US12994113
申请日：2009-05-11
IPC分类号： H01L21/33 , H01L29/732
CPC分类号： H01L29/7378 , H01L29/66242
摘要： Methods for manufacturing a bipolar transistor semiconductor device are described, along with devices fabricated in accordance with the methods. The methods include the steps of forming a stack of layers over a semiconductor body comprising a window definition layer (18,38), a layer (20) of semiconductor material, a first insulating layer (22), and a second insulating layer (24) which is selectively etchable with respect to the first insulating layer. A trench (26) is then etched into the stack down to the window definition layer. The portion of the trench extending through the second insulating layer is widened to form a wider trench portion (28) therethrough. A window (36) is defined in the window definition layer which is aligned with the wider trench portion, and serves to define the base-collector or base-emitter junction in the finished device.
摘要翻译： 描述了制造双极晶体管半导体器件的方法以及根据该方法制造的器件。 所述方法包括以下步骤：在半导体主体上形成层叠层，其包括窗口界定层（18,38），半导体材料层（20），第一绝缘层（22）和第二绝缘层（24） ），其相对于第一绝缘层可选择性地蚀刻。 然后将沟槽（26）蚀刻到堆叠中，直到窗口定义层。 延伸穿过第二绝缘层的沟槽的部分被加宽以形成穿过其中的较宽的沟槽部分（28）。 在窗口定义层中限定窗口（36），其与较宽的沟槽部分对准，并且用于限定最终器件中的基极 - 集电极或基极 - 发射极结。
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公开(公告)号：US08476675B2
公开(公告)日：2013-07-02
申请号：US12918524
申请日：2009-02-26
IPC分类号： H01L29/66
CPC分类号： H01L21/8249 , H01L27/0623 , H01L29/0649 , H01L29/0821 , H01L29/1004 , H01L29/165 , H01L29/42304 , H01L29/456 , H01L29/66242 , H01L29/7378
摘要： A semiconductor device (10) comprising a bipolar transistor and a field 5 effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22c and 22d) and a base region (33c) of the bipolar transistor. The bipolar transistor is provided with an insulating cavity (92b) provided in the collector region (22c and 22d). The insulating cavity (92b) may be provided by providing a layer (33a) in the collector region (22c), creating an access path, for example by selectively etching polysilicon towards monocrystalline, and removing a portion of the layer (33a) to provide the cavity using the access path. The layer (33a) provided in the collector region may be of SiGe:C. By blocking diffusion from the base region the insulating cavity (92b) provides a reduction in the base collector capacitance and can be described as defining the base contact.
摘要翻译： 一种半导体器件（10），包括在半导体本体（1）内的双极晶体管和场效应晶体管，包括突出的台面（5），其中集电极区域（22c和22d）的至少一部分和基极区域 （33c）。 双极晶体管设置有设置在集电区域（22c和22d）中的绝缘腔（92b）。 可以通过在集电极区域（22c）中设置层（33a）来提供绝缘腔（92b），从而产生存取路径，例如通过选择性地将多晶硅蚀刻成单晶，并去除层（33a）的一部分以提供 使用进入路径的空腔。 设置在集电区域中的层（33a）可以是SiGe：C。 通过阻挡从基极区域的扩散，绝缘腔（92b）提供基极集电极电容的减小，并且可以被描述为限定基极接触。
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公开(公告)号：US07605027B2
公开(公告)日：2009-10-20
申请号：US11913049
申请日：2006-04-24
CPC分类号： H01L29/66272 , H01L29/0821
摘要： A method of fabricating a bipolar transistor in a first trench (11) is disclosed wherein only one photolithographic mask is applied which forms a first trench (11) and a second trench (12). A collector region (21) is formed self-aligned in the first trench (11) and the second trench (12). A base region (31) is formed self-aligned on a portion of the collector region (21), which is in the first trench (11). An emitter region (41) is formed self-aligned on a portion of the base region (31). A contact to the collector region (21) is formed in the second trench (12) and a contact to the base region (31) is formed in the first trench (11). The fabrication of the bipolar transistor may be integrated in a standard CMOS process.
摘要翻译： 公开了在第一沟槽（11）中制造双极晶体管的方法，其中仅施加一个形成第一沟槽（11）和第二沟槽（12）的光刻掩模。 集电极区域（21）在第一沟槽（11）和第二沟槽（12）中自对准地形成。 基部区域（31）在位于第一沟槽（11）中的集电极区域（21）的一部分上自对准地形成。 发射极区域（41）在基极区域（31）的一部分上自对准地形成。 在所述第二沟槽（12）中形成与所述集电极区域（21）的接触，并且在所述第一沟槽（11）中形成与所述基部区域（31）的接触。 双极晶体管的制造可以集成在标准CMOS工艺中。
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8.发明授权Gringo heterojunction bipolar transistor with a metal extrinsic base region 有权具有金属外在基极区域的Gringo异质结双极晶体管公开(公告)号：US09041149B2
公开(公告)日：2015-05-26
申请号：US13059277
申请日：2009-08-05
申请人： Guillaume Boccardi , Mark C. J. C. M. Kramer , Johannes J. T. M. Donkers , Li Jen Choi , Stefaan Decoutere , Arturo Sibaja-Hernandez , Stefaan Van Huylenbroeck , Rafael Venegas
发明人： Guillaume Boccardi , Mark C. J. C. M. Kramer , Johannes J. T. M. Donkers , Li Jen Choi , Stefaan Decoutere , Arturo Sibaja-Hernandez , Stefaan Van Huylenbroeck , Rafael Venegas
IPC分类号： H01L21/70 , H01L29/10 , H01L21/8249 , H01L27/06 , H01L29/66
CPC分类号： H01L29/1004 , H01L21/8249 , H01L27/0623 , H01L29/66242 , H01L29/66287
摘要： The invention relates to a semiconductor device (30) comprising a substrate (1), a semiconductor body (25) comprising a bipolar transistor that comprises a collector region (3), a base region (4), and an emitter region (15), wherein at least a portion of the collector region (3) is surrounded by a first isolation region (2, 8), the semiconductor body (25) further comprises an extrinsic base region (35) arranged in contacting manner to the base region (4). In this way, a fast semiconductor device with reduced impact of parasitic components is obtained.
摘要翻译： 本发明涉及一种包括基板（1）的半导体器件（30），包括集电极区（3），基极区（4）和发射极区（15））的双极晶体管的半导体本体（25） ，其中所述集电极区域（3）的至少一部分被第一隔离区域（2,8）包围，所述半导体本体（25）还包括以与所述基极区域接触的方式布置的外部基极区域（35） 4）。 以这种方式，获得了具有减小的寄生分量影响的快速半导体器件。
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公开(公告)号：US08481365B2
公开(公告)日：2013-07-09
申请号：US12995100
申请日：2009-05-19
CPC分类号： B81C1/00293 , B81C2203/0145
摘要： A method of manufacturing a MEMS device comprises forming a MEMS device element (14). A sacrificial layer (20) is provided over the device element and a package cover layer (22) is provided over the sacrificial layer. The sacrificial layer is removed using at least one opening (22) in the cover layer and the at least one opening (24) is sealed by an anneal process.
摘要翻译： 制造MEMS器件的方法包括形成MEMS器件元件（14）。 牺牲层（20）设置在器件元件上方，并且封装覆盖层（22）设置在牺牲层上。 使用覆盖层中的至少一个开口（22）去除牺牲层，并且通过退火工艺密封至少一个开口（24）。
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10.发明授权Method of manufacturing a bipolar transistor and bipolar transistor obtained therewith 有权制造双极晶体管的方法和由其获得的双极晶体管公开(公告)号：US08133791B2
公开(公告)日：2012-03-13
申请号：US12306653
申请日：2007-06-12
IPC分类号： H01L21/331
CPC分类号： H01L29/66287 , H01L29/66242
摘要： The invention relates to a method according to the part of the surface of the semiconductor body adjoining the opening and which is to be kept free is provided with a cover layer after which the high-crystalline layer is formed by means of a deposition process. The material of the cover layer can then easily be chosen such that it can be selectively etched relative to the silicon underneath. In addition, the cover layer can easily be selectively deposited on the relevant part of the surface because use can be made of an anisotropic deposition process. In such a process the cover layer is not deposited in the hollow and on the bottom of the hollow. It will be apparent that for the high-crystalline layer also other materials can be chosen such as SiGe having such low Ge contents that the SiGe cannot be etched selectively very well compared to the Silicon.
摘要翻译： 本发明涉及一种根据与开口相邻的半导体主体的表面部分的方法，该方法要保持自由，该覆盖层之后通过沉积工艺形成高结晶层。 然后可以容易地选择覆盖层的材料，使得其可以相对于下面的硅选择性地被蚀刻。 此外，可以容易地将覆盖层选择性地沉积在表面的相关部分上，因为可以使用各向异性沉积工艺。 在这种过程中，覆盖层不会沉积在中空部分的中空部分和底部中。 显而易见的是，对于高结晶层，还可以选择其他材料，例如具有如此低Ge含量的SiGe，与硅相比，SiGe不能被选择性地非常好地蚀刻。
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