公开(公告)号：US06956238B2

公开(公告)日：2005-10-18

申请号：US09911995

申请日：2001-07-24

申请人： Sei-Hyung Ryu ,  Anant Agarwal ,  Mrinal Kanti Das ,  Lori A. Lipkin ,  John W. Palmour ,  Ranbir Singh

发明人： Sei-Hyung Ryu ,  Anant Agarwal ,  Mrinal Kanti Das ,  Lori A. Lipkin ,  John W. Palmour ,  Ranbir Singh

IPC分类号： H01L21/04 ,  H01L21/336 ,  H01L29/10 ,  H01L29/12 ,  H01L29/24 ,  H01L29/78 ,  H01L29/161

CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7828 ,  H01L29/7838

摘要： Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) and methods of fabricating silicon carbide MOSFETs are provided. The silicon carbide MOSFETs have an n-type silicon carbide drift layer, spaced apart p-type silicon carbide regions in the n-type silicon carbide drift layer and having n-type silicon carbide regions therein, and a nitrided oxide layer. The MOSFETs also have n-type shorting channels extending from respective ones of the n-type silicon carbide regions through the p-type silicon carbide regions to the n-type silicon carbide drift layer. In further embodiments, silicon carbide MOSFETs and methods of fabricating silicon carbide MOSFETs are provided that include a region that is configured to self-deplete the source region, between the n-type silicon carbide regions and the drift layer, adjacent the oxide layer, upon application of a zero gate bias.

摘要翻译： 提供了碳化硅金属氧化物半导体场效应晶体管（MOSFET）和制造碳化硅MOSFET的方法。 碳化硅MOSFET具有n型碳化硅漂移层，n型碳化硅漂移层中间隔开的p型碳化硅区域，其中具有n型碳化硅区域和氮化氧化物层。 MOSFET还具有从n型碳化硅区域中的相应的n型碳化硅区域延伸穿过p型碳化硅区域到n型碳化硅漂移层的n型短路通道。 在另外的实施例中，提供了碳化硅MOSFET和制造碳化硅MOSFET的方法，其包括被配置为在n型碳化硅区域和与氧化物层相邻的漂移层之间自耗光源区域的区域 零门偏置的应用。

公开(公告)号：US06514779B1

公开(公告)日：2003-02-04

申请号：US09981523

申请日：2001-10-17

申请人： Sei-Hyung Ryu ,  Anant Agarwal ,  Craig Capell ,  John W. Palmour

发明人： Sei-Hyung Ryu ,  Anant Agarwal ,  Craig Capell ,  John W. Palmour

IPC分类号： G01R3126

CPC分类号： G01R31/2831 ,  H01L22/22 ,  H01L2924/0002 ,  H01L2924/00

摘要： A silicon carbide device is fabricated by forming a plurality of a same type of silicon carbide devices on at least a portion of a silicon carbide wafer in a predefined pattern. The silicon carbide devices have corresponding first contacts on a first face of the silicon carbide wafer. The plurality of silicon carbide devices are electrically, tested to identify ones of the plurality of silicon carbide devices which pass an electrical test. The first contact of the identified ones of the silicon carbide devices are then selectively interconnected. Devices having a plurality of selectively connected silicon carbide devices of the same type are also provided.

摘要翻译： 通过在预定图案的碳化硅晶片的至少一部分上形成多个相同类型的碳化硅器件来制造碳化硅器件。 碳化硅器件在碳化硅晶片的第一面上具有对应的第一接触。 多个碳化硅器件被电学测试以识别通过电测试的多个碳化硅器件中的一个。 所识别的碳化硅器件的第一接触然后被选择性地互连。 还提供了具有相同类型的多个选择性连接的碳化硅器件的器件。

公开(公告)号：US06770911B2

公开(公告)日：2004-08-03

申请号：US09952064

申请日：2001-09-12

申请人： Anant Agarwal ,  Sei-Hyung Ryu ,  John W. Palmour

发明人： Anant Agarwal ,  Sei-Hyung Ryu ,  John W. Palmour

IPC分类号： H01L29417

CPC分类号： H01L31/1113 ,  Y10S438/931

摘要： Large area silicon carbide devices, such as light-activated silicon carbide thyristors, having only two terminals are provided. The silicon carbide devices are selectively connected in parallel by a connecting plate. Silicon carbide thyristors are also provided having a portion of the gate region of the silicon carbide thyristors exposed so as to allow light of an energy greater than about 3.25 eV to activate the gate of the thyristor. The silicon carbide thyristors may be symmetric or asymmetrical. A plurality of the silicon carbide thyristors may be formed on a wafer, a portion of a wafer or multiple wafers. Bad cells may be determined and the good cells selectively connected by a connecting plate.

摘要翻译： 提供仅具有两个端子的大面积碳化硅器件，例如光激活碳化硅晶闸管。 碳化硅器件通过连接板选择性地并联连接。 还提供了碳化硅晶闸管，其具有暴露的碳化硅晶闸管的栅极区域的一部分，以允许大于约3.25eV的能量的光来激活晶闸管的栅极。 碳化硅晶闸管可以是对称的或不对称的。 多个碳化硅晶闸管可以形成在晶片，晶片的一部分或多个晶片上。 可以确定坏细胞，并且通过连接板选择性地连接良好的细胞。

公开(公告)号：US07135359B2

公开(公告)日：2006-11-14

申请号：US10845913

申请日：2004-05-14

申请人： Anant Agarwal ,  Sei-Hyung Ryu ,  John W. Palmour

发明人： Anant Agarwal ,  Sei-Hyung Ryu ,  John W. Palmour

IPC分类号： H01L21/332

CPC分类号： H01L31/1113 ,  Y10S438/931

摘要： Large area silicon carbide devices, such as light-activated silicon carbide thyristors, having only two terminals are provided. The silicon carbide devices are selectively connected in parallel by a connecting plate. Silicon carbide thyristors are also provided having a portion of the gate region of the silicon carbide thyristors exposed so as to allow light of an energy greater than about 3.25 eV to activate the gate of the thyristor. The silicon carbide thyristors may be symmetric or asymmetrical. A plurality of the silicon carbide thyristors may be formed on a wafer, a portion of a wafer or multiple wafers. Bad cells may be determined and the good cells selectively connected by a connecting plate.

摘要翻译： 提供仅具有两个端子的大面积碳化硅器件，例如光激活碳化硅晶闸管。 碳化硅器件通过连接板选择性地并联连接。 还提供了碳化硅晶闸管，其具有暴露的碳化硅晶闸管的栅极区域的一部分，以允许大于约3.25eV的能量的光来激活晶闸管的栅极。 碳化硅晶闸管可以是对称的或不对称的。 多个碳化硅晶闸管可以形成在晶片，晶片的一部分或多个晶片上。 可以确定坏细胞，并且通过连接板选择性地连接良好的细胞。

公开(公告)号：US07883949B2

公开(公告)日：2011-02-08

申请号：US11740687

申请日：2007-04-26

申请人： Mrinal Kanti Das ,  Qingchun Zhang ,  Sei-Hyung Ryu

发明人： Mrinal Kanti Das ,  Qingchun Zhang ,  Sei-Hyung Ryu

IPC分类号： H01L21/337

CPC分类号： H01L21/324 ,  H01L21/046 ,  H01L21/049 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7838 ,  Y10S438/931

摘要： Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is formed in the channel region. The implanted ions are annealed in an inert atmosphere at a temperature greater than 1650° C. A gate oxide layer is formed on the channel region, and a gate is formed on the gate oxide layer. A silicon carbide-based transistor includes a silicon carbide layer, an n-type well in the silicon carbide layer, and a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is in the channel region and includes p-type dopants at a dopant concentration of about 1×1016 cm−3 to about 5×1018 cm−3. The transistor further includes a gate oxide layer on the channel region, and a gate on the gate oxide layer. The transistor may exhibit a hole mobility in the channel region in excess of 5 cm2/V-s at a gate voltage of −25V.

摘要翻译： 在碳化硅中形成p沟道MOS器件的方法包括在碳化硅层中形成n型阱，以及注入p型掺杂离子以在n型阱的表面形成p型区域 并且在邻近p型区域的n型阱中至少部分地限定沟道区。 在通道区域中形成阈值调整区域。 注入的离子在惰性气氛中在大于1650℃的温度下进行退火。在沟道区上形成栅极氧化层，栅极氧化层上形成栅极。 基于碳化硅的晶体管包括碳化硅层，碳化硅层中的n型阱以及在碳化硅层的表面处的n型阱中的p型区域，并且至少部分地限定沟道 邻近p型区域的n型阱区域。 阈值调整区域在通道区域中，并且包括掺杂剂浓度为约1×10 16 cm -3至约5×10 18 cm -3的p型掺杂剂。 晶体管还包括在沟道区上的栅极氧化层和栅极氧化物层上的栅极。 晶体管可以在-25V的栅极电压下在沟道区中表现出超过5cm 2 / V-s的空穴迁移率。

公开(公告)号：US20110121318A1

公开(公告)日：2011-05-26

申请号：US13019723

申请日：2011-02-02

申请人： Mrinal Kanti Das ,  Qingchun Zhang ,  Sei-Hyung Ryu

发明人： Mrinal Kanti Das ,  Qingchun Zhang ,  Sei-Hyung Ryu

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L21/324 ,  H01L21/046 ,  H01L21/049 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7838 ,  Y10S438/931

摘要： Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is formed in the channel region. The implanted ions are annealed in an inert atmosphere at a temperature greater than 1650° C. A gate oxide layer is formed on the channel region, and a gate is formed on the gate oxide layer. A silicon carbide-based transistor includes a silicon carbide layer, an n-type well in the silicon carbide layer, and a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is in the channel region and includes p-type dopants at a dopant concentration of about 1×1016 cm−3 to about 5×1018 cm−3. The transistor further includes a gate oxide layer on the channel region, and a gate on the gate oxide layer. The transistor may exhibit a hole mobility in the channel region in excess of 5 cm2/V-s at a gate voltage of −25V.

摘要翻译： 在碳化硅中形成p沟道MOS器件的方法包括在碳化硅层中形成n型阱，以及注入p型掺杂离子以在n型阱的表面形成p型区域 并且在邻近p型区域的n型阱中至少部分地限定沟道区。 在通道区域中形成阈值调整区域。 注入的离子在惰性气氛中在大于1650℃的温度下进行退火。在沟道区上形成栅极氧化层，栅极氧化层上形成栅极。 基于碳化硅的晶体管包括碳化硅层，碳化硅层中的n型阱以及在碳化硅层的表面处的n型阱中的p型区域，并且至少部分地限定沟道 邻近p型区域的n型阱区域。 阈值调整区域在通道区域中，并且包括掺杂剂浓度为约1×10 16 cm -3至约5×10 18 cm -3的p型掺杂剂。 晶体管还包括在沟道区上的栅极氧化层和栅极氧化物层上的栅极。 晶体管可以在-25V的栅极电压下在沟道区中表现出超过5cm 2 / V-s的空穴迁移率。

公开(公告)号：US20080001158A1

公开(公告)日：2008-01-03

申请号：US11740687

申请日：2007-04-26

申请人： Mrinal Kanti Das ,  Qingchun Zhang ,  Sei-Hyung Ryu

发明人： Mrinal Kanti Das ,  Qingchun Zhang ,  Sei-Hyung Ryu

IPC分类号： H01L29/12 ,  H01L21/336

CPC分类号： H01L21/324 ,  H01L21/046 ,  H01L21/049 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7838 ,  Y10S438/931

摘要： Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is formed in the channel region. The implanted ions are annealed in an inert atmosphere at a temperature greater than 1650° C. A gate oxide layer is formed on the channel region, and a gate is formed on the gate oxide layer. A silicon carbide-based transistor includes a silicon carbide layer, an n-type well in the silicon carbide layer, and a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is in the channel region and includes p-type dopants at a dopant concentration of about 1×1016 cm−3 to about 5×1018 cm−3. The transistor further includes a gate oxide layer on the channel region, and a gate on the gate oxide layer. The transistor may exhibit a hole mobility in the channel region in excess of 5 cm2/V-s at a gate voltage of −25V.

摘要翻译： 在碳化硅中形成p沟道MOS器件的方法包括在碳化硅层中形成n型阱，以及注入p型掺杂离子以在n型阱的表面形成p型区域 并且在邻近p型区域的n型阱中至少部分地限定沟道区。 在通道区域中形成阈值调整区域。 注入的离子在惰性气氛中在大于1650℃的温度下进行退火。在沟道区上形成栅极氧化层，栅极氧化层上形成栅极。 基于碳化硅的晶体管包括碳化硅层，碳化硅层中的n型阱以及在碳化硅层的表面处的n型阱中的p型区域，并且至少部分地限定沟道 邻近p型区域的n型阱区域。 阈值调整区域在通道区域中，并且包括掺杂剂浓度为约1×10 16 -3 -3至约5×10 18 /小时的p型掺杂剂 > cm 3 -3。 晶体管还包括在沟道区上的栅极氧化层和栅极氧化物层上的栅极。 晶体管可以在-25V的栅极电压下在沟道区中显示超过5cm 2 / V-s的空穴迁移率。

公开(公告)号：US09552997B2

公开(公告)日：2017-01-24

申请号：US13019723

申请日：2011-02-02

申请人： Mrinal Kanti Das ,  Qingchun Zhang ,  Sei-Hyung Ryu

发明人： Mrinal Kanti Das ,  Qingchun Zhang ,  Sei-Hyung Ryu

IPC分类号： H01L21/02 ,  H01L29/02 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/324 ,  H01L21/04 ,  H01L29/16 ,  H01L29/739 ,  H01L29/04

CPC分类号： H01L21/324 ,  H01L21/046 ,  H01L21/049 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7838 ,  Y10S438/931

摘要： Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is formed in the channel region. The implanted ions are annealed in an inert atmosphere at a temperature greater than 1650° C. A gate oxide layer is formed on the channel region, and a gate is formed on the gate oxide layer. A silicon carbide-based transistor includes a silicon carbide layer, an n-type well in the silicon carbide layer, and a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is in the channel region and includes p-type dopants at a dopant concentration of about 1×1016 cm−3 to about 5×1018 cm−3. The transistor further includes a gate oxide layer on the channel region, and a gate on the gate oxide layer. The transistor may exhibit a hole mobility in the channel region in excess of 5 cm2/V-s at a gate voltage of −25V.

摘要翻译： 在碳化硅中形成p沟道MOS器件的方法包括在碳化硅层中形成n型阱，以及注入p型掺杂离子以在n型阱的表面形成p型区域 并且在邻近p型区域的n型阱中至少部分地限定沟道区。 在通道区域中形成阈值调整区域。 注入的离子在惰性气氛中在大于1650℃的温度下进行退火。在沟道区上形成栅极氧化层，栅极氧化层上形成栅极。 基于碳化硅的晶体管包括碳化硅层，碳化硅层中的n型阱以及在碳化硅层的表面处的n型阱中的p型区域，并且至少部分地限定沟道 邻近p型区域的n型阱区域。 阈值调整区域在通道区域中，并且包括掺杂剂浓度为约1×10 16 cm -3至约5×10 18 cm -3的p型掺杂剂。 晶体管还包括在沟道区上的栅极氧化层和栅极氧化物层上的栅极。 晶体管可以在-25V的栅极电压下在沟道区中表现出超过5cm 2 / V-s的空穴迁移率。

公开(公告)号：US07705362B2

公开(公告)日：2010-04-27

申请号：US11513473

申请日：2006-08-31

申请人： Mrinal Kanti Das ,  Sei-Hyung Ryu

发明人： Mrinal Kanti Das ,  Sei-Hyung Ryu

IPC分类号： H01L31/0312

CPC分类号： H01L29/7802 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  Y10S438/931

摘要： MOS channel devices and methods of fabricating such devices having a hybrid channel are provided. Exemplary devices include vertical power MOSFETs that include a hybrid well region of silicon carbide and methods of fabricating such devices are provided. The hybrid well region may include an implanted p-type silicon carbide well portion in a p-type silicon carbide epitaxial layer, an implanted p-type silicon carbide contact portion that contacts the implanted p-type silicon carbide well portion and extends to a surface of the p-type epitaxial layer and/or an epitaxial p-type silicon carbide portion, at least a portion of the epitaxial p-type silicon carbide well portion corresponding to a p-type channel region of the MOSFET.

摘要翻译： 提供了MOS通道器件和制造具有混合通道的器件的方法。 示例性器件包括垂直功率MOSFET，其包括碳化硅的混合阱区域以及制造这种器件的方法。 混合阱区可以包括在p型碳化硅外延层中注入的p型碳化硅阱部分，注入的p型碳化硅接触部分，其与注入的p型碳化硅阱部分接触并延伸到表面 的p型外延层和/或外延p型碳化硅部分的至少一部分，所述外延p型碳化硅阱部分的至少一部分对应于所述MOSFET的p型沟道区。

公开(公告)号：US07118970B2

公开(公告)日：2006-10-10

申请号：US10873394

申请日：2004-06-22

申请人： Mrinal Kanti Das ,  Sei-Hyung Ryu

发明人： Mrinal Kanti Das ,  Sei-Hyung Ryu

IPC分类号： H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  Y10S438/931

摘要： MOS channel devices and methods of fabricating such devices having a hybrid channel are provided. Exemplary devices include vertical power MOSFETs that include a hybrid well region of silicon carbide and methods of fabricating such devices are provided. The hybrid well region may include an implanted p-type silicon carbide well portion in a p-type silicon carbide epitaxial layer, an implanted p-type silicon carbide contact portion that contacts the implanted p-type silicon carbide well portion and extends to a surface of the p-type epitaxial layer and/or an epitaxial p-type silicon carbide portion, at least a portion of the epitaxial p-type silicon carbide well portion corresponding to a p-type channel region of the MOSFET.

摘要翻译： 提供了MOS通道器件和制造具有混合通道的器件的方法。 示例性器件包括垂直功率MOSFET，其包括碳化硅的混合阱区域以及制造这种器件的方法。 混合阱区可以包括在p型碳化硅外延层中注入的p型碳化硅阱部分，注入的p型碳化硅接触部分，其与注入的p型碳化硅阱部分接触并延伸到表面 的p型外延层和/或外延p型碳化硅部分的至少一部分，所述外延p型碳化硅阱部分的至少一部分对应于所述MOSFET的p型沟道区。