公开(公告)号：US10741682B2

公开(公告)日：2020-08-11

申请号：US15807237

申请日：2017-11-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul Jeon ,  Ali Salih ,  Llewellyn Vaughan-Edmunds

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/08 ,  H01L29/872 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10

Abstract: High-electron-mobility transistor (HEMT) devices are described in this patent application. In some implementations, the HEMT devices can include a back barrier hole injection structure. In some implementations, the HEMT devices include a conductive striped portion electrically coupled to a drain contact.

公开(公告)号：US10854718B2

公开(公告)日：2020-12-01

申请号：US15438675

申请日：2017-02-21

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul Jeon

IPC: H01L29/861 ,  H01L29/20 ,  H01L27/07 ,  H01L27/02 ,  H01L29/205 ,  H01L21/8252 ,  H01L27/06

Abstract: In one embodiment, a method of forming a HEM diode may comprise forming the HEM diode with high forward voltage that is greater than one of a gate-to-source threshold voltage of a HEMT or a forward voltage of a P-N diode.

公开(公告)号：US11769807B2

公开(公告)日：2023-09-26

申请号：US16948788

申请日：2020-10-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul Jeon

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L29/41758 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/2003

Abstract: Semiconductor devices, such as a lateral HEMT, may display current flow between a plurality of interdigitated source fingers and drain fingers, and controlled by a common gate connection. An extended source finger contact may enable improved voltage control across the source fingers, even for large devices with many and/or lengthy source fingers. In this way, unwanted subthreshold operations and switching oscillations may be avoided by reliably maintaining a source voltage at a desired level, to thereby provide fast and reliable switching.

公开(公告)号：US11538931B2

公开(公告)日：2022-12-27

申请号：US16947593

申请日：2020-08-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul Jeon ,  Ali Salih ,  Llewellyn Vaughan-Edmunds

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/08 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10 ,  H01L29/872

Abstract: A semiconductor device includes a carrier generation layer disposed on a channel layer, a source contact and a drain contact disposed on the carrier generation layer, and a gate contact disposed between the source contact and the drain contact. The semiconductor device further includes a number N of conductive stripes disposed directly on the carrier generation layer in an area between the drain contact and the gate contact, and a number M of conductive transverse stripes disposed directly on the carrier generation layer in the area between the drain contact and the gate contact. Each of the N conductive stripes extends from and is electrically coupled to the drain contact. Each of the M conductive transverse stripes is aligned non-parallel to the N conductive stripes and is not in direct physical contact with the N conductive stripes.

公开(公告)号：US10559678B2

公开(公告)日：2020-02-11

申请号：US15911999

申请日：2018-03-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul Jeon ,  ALi Salih

IPC: H01L29/778 ,  H01L49/02 ,  H01L29/40 ,  H01L27/088 ,  H01L29/20

Abstract: In an aspect, a cascode circuit can include a high-side transistor and a low-side transistor. The source of the high-side transistor can be coupled to the drain of the low-side transistor; and the gate of the high-side transistor can be coupled to each of the source and the gate of the low-side transistor. In another aspect, an electronic device can include a high-side transistor, a low-side transistor, and a field electrode. The low-side transistor can include a drain region coupled to the source electrode of the high-side transistor. The field electrode can overlie and be capacitively coupled to a channel layer of the high-side transistor, wherein the field electrode is configured to be at a voltage between the voltages of the high-side and low-side power supply terminals.

公开(公告)号：US20190305123A1

公开(公告)日：2019-10-03

申请号：US16287400

申请日：2019-02-27

Applicant: Semiconductor Components Industries, LLC

Inventor： Woochul Jeon ,  Balaji Padmanabhan

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L27/06 ,  H03K17/687

Abstract: An electronic device can include an enhancement-mode high electron mobility transistor (HEMT) that includes a source electrode; a drain electrode; and a gate. In an embodiment, the gate can correspond to spaced-apart gate electrodes and a space disposed between the spaced-apart gate electrodes, wherein the first space has a width configured such that, a continuous depletion region forms across all of the width of the first space. In another embodiment, the gate can be a gate electrode having a nonuniform thickness along a line in a gate width direction. In another aspect, a method of using the electronic device can include, during a transient period when the HEMT is in an off-state, flowing current from the drain electrode to the source electrode when Vds>−Vth+Vgs.

公开(公告)号：US10217737B2

公开(公告)日：2019-02-26

申请号：US15648264

申请日：2017-07-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji Padmanabhan ,  Prasad Venkatraman ,  Zia Hossain ,  Chun-Li Liu ,  Woochul Jeon ,  Jason Mcdonald

IPC: H01L29/66 ,  H01L27/06 ,  H01L27/02 ,  H01L23/367 ,  H01L29/417 ,  H01L29/778 ,  H01L29/10 ,  H01L21/8258 ,  H01L21/74 ,  H01L29/872 ,  H01L23/48 ,  H01L29/861 ,  H01L29/20

Abstract: In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A rectifier device is integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes. The cascode rectifier structure is configured as a two terminal device.

公开(公告)号：US10069002B2

公开(公告)日：2018-09-04

申请号：US15214579

申请日：2016-07-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul Jeon ,  Chun-Li Liu

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/417 ,  H01L23/535

Abstract: Implementations of semiconductor devices may include: a first layer with a plurality of cells, each cell having a drain finger, a source finger and a gate ring; a second layer having a drain pad and a source pad, the drain pad having a width and a source pad having a width substantially the same as the drain pad; wherein a width of each drain finger of the first layer is wider than a width of each source finger of the first layer; and wherein each drain pad is coupled to each drain finger through a first contact and the source pad is coupled to each source finger through a second contact, where a width of the first contact is wider than a width of the second contact.

公开(公告)号：US10797153B2

公开(公告)日：2020-10-06

申请号：US16025085

申请日：2018-07-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Abhishek Banerjee ,  Piet Vanmeerbeek ,  Peter Moens ,  Marnix Tack ,  Woochul Jeon ,  Ali Salih

IPC: H01L21/338 ,  H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20

Abstract: A process of forming an electronic device can include forming a channel layer overlying a substrate and forming a barrier layer overlying the channel layer. In an embodiment, the process can further include forming a p-type semiconductor layer over the barrier layer, patterning the p-type semiconductor layer to define at least part of a gate electrode of a transistor structure, and forming an access region layer over the barrier layer. In another embodiment, the process can further include forming an etch-stop layer over the barrier layer, forming a sacrificial layer over the etch-stop layer, patterning the etch-stop and sacrificial layers to define a gate region, forming an access region layer over the barrier layer after patterning the etch-stop and sacrificial layers, and forming a p-type semiconductor layer within the gate region.

公开(公告)号：US10741653B2

公开(公告)日：2020-08-11

申请号：US16569218

申请日：2019-09-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul Jeon ,  Chun-Li Liu

IPC: H01L29/417 ,  H01L29/778 ,  H01L29/20 ,  H01L23/535 ,  H01L23/482 ,  H01L29/423

Abstract: Implementations of semiconductor devices may include: a first layer with a plurality of cells, each cell having a drain finger, a source finger and a gate ring; a second layer having a drain pad and a source pad, the drain pad having a width and a source pad having a width substantially the same as the drain pad; wherein a width of each drain finger of the first layer is wider than a width of each source finger of the first layer; and wherein each drain pad is coupled to each drain finger through a first contact and the source pad is coupled to each source finger through a second contact, where a width of the first contact is wider than a width of the second contact.