Abstract:
In a general aspect, a semiconductor device can include a semiconductor region of a first conductivity type and a well region of a second conductivity type. The well region can be disposed in the semiconductor region. An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The semiconductor device can further include at least one dielectric region disposed in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.
Abstract:
A semiconductor device structure includes a region of semiconductor material having an active region and a termination region. An active structure is disposed in the active region and a termination structure is disposed in the termination region. In one embodiment, the termination structure includes a termination trench and a conductive structure within the termination trench and electrically isolated from the region of semiconductor material by a dielectric structure. A dielectric layer is disposed to overlap the termination trench to provide the termination structure as a floating structure. A Schottky contact region is disposed within the active region. A conductive layer is electrically connected to the Schottky contact region and the first conductive layer extends onto a surface of the dielectric layer and laterally overlaps at least a portion of the termination trench.
Abstract:
In one embodiment, a group III-V transistor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A clamping device is integrated with the group III-V transistor structure and is electrically connected to the first current carrying electrode a third electrode to provide a secondary current path during, for example, an electrical stress event.
Abstract:
An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface. The electronic device can further include first conductive structures within each of a first trench and a second trench, a gate electrode within the first trench and electrically insulated from the first conductive structure, a first insulating member disposed between the gate electrode and the first conductive structure within the first trench, and a second conductive structure within the second trench. The second conductive structure can be electrically connected to the first conductive structures and is electrically insulated from the gate electrode. The electronic device can further include a second insulating member disposed between the second conductive structure and the first conductive structure within the second trench. Processing sequences can be used that simplify formation of the features within the electronic device.
Abstract:
A semiconductor device includes a semiconductor region with a charge balance region on a junction blocking region, which has a lower doping concentration. A trench structure having an insulated shield electrode and an insulated gate electrode is provided in the semiconductor region. The semiconductor device further includes one or more features configured to improve operating performance. The features include terminating the trench structure in the junction blocking region, providing a localized doped region adjoining a lower surface of a body region and spaced apart from the trench structure, disposing a notch proximate to the lower surface of the body region, and/or configuring the insulated shield electrode to have a wide portion adjoining a narrow portion.
Abstract:
In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor.
Abstract:
An electronic device can include a substrate, an active region of a transistor, and a shield electrode. The substrate can define a trench and include a mesa adjacent to the trench, and the shield electrode can be within the trench. In an embodiment, the electronic device can further include an active region of a transistor within the mesa and an insulating layer including a thicker section and a thinner section closer to a bottom of the trench. In another embodiment, the electronic device can include a body region and a doped region within the mesa and spaced apart from the body region by a semiconductor region. The doped region can have a dopant concentration that is higher than a dopant concentration of the semiconductor region and a portion of the substrate underlying the doped region.
Abstract:
A semiconductor device structure includes a region of semiconductor material having an active region and a termination region. An active structure is disposed in the active region and a termination structure is disposed in the termination region. In one embodiment, the termination structure includes a termination trench and a conductive structure within the termination trench and electrically isolated from the region of semiconductor material by a dielectric structure. A dielectric layer is disposed to overlap the termination trench to provide the termination structure as a floating structure. A Schottky contact region is disposed within the active region. A conductive layer is electrically connected to the Schottky contact region and the first conductive layer extends onto a surface of the dielectric layer and laterally overlaps at least a portion of the termination trench.