-
公开(公告)号：US12118333B2
公开(公告)日：2024-10-15
申请号：US17050359
申请日：2019-04-15
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Takayuki Ikeda , Roh Yamamoto , Shuichi Katsui
CPC classification number: G06F7/60 , G06F7/57 , G06N3/08 , H01L27/1207 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L29/78648 , H01L29/7869 , H10B12/00
Abstract: A semiconductor device that updates a weight coefficient used for arithmetic operation by an artificial neural network is provided. Each of the first to third memory cells draws a current corresponding to data of its retention node and changes the data in accordance with the potentials of first and second wirings. When a weight coefficient and first and second reference data are held in the retention nodes of the first to third memory cells, the first circuit supplies, to a third wiring, a constant currents drawn by the second and third memory cells. When input data is input to the first wiring, a difference current between the constant current and a current drawn by the first memory cell is changed, and the second circuit outputs arithmetic result data corresponding to the change. The third circuit inputs update data corresponding to the arithmetic result data to the second wiring.
-
公开(公告)号：US09507366B2
公开(公告)日：2016-11-29
申请号：US13801091
申请日：2013-03-13
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Kei Takahashi , Masaaki Hiroki , Takehisa Sato , Roh Yamamoto
CPC classification number: G05F5/00 , H02J9/00 , H02M2001/008
Abstract: An object is to reduce standby power in a data processing device, without loss of convenience, in a structure in which a power supply control device includes the data processing device. In a structure of a power supply control device which supplies power to an external device using a main switch, a data processing device is provided in the power supply control device to control the main switch; a sub-switch supplying power to the data processing device is provided; and a volatile memory unit and a nonvolatile memory unit are provided in the data processing device. Further, the sub-switch is off in a period in which data is stored in the nonvolatile memory unit of the data processing device, so that power supply to the data processing device is intermittently stopped.
Abstract translation: 在电源控制装置包括数据处理装置的结构中，目的在于减少数据处理装置中的待机功率，而不损失便利性。 在使用主开关向外部装置供电的电源控制装置的结构中，在电源控制装置中设置有数据处理装置，以控制主开关; 提供向数据处理装置供电的子开关; 并且在数据处理装置中设置易失性存储器单元和非易失性存储器单元。 此外，在数据存储在数据处理装置的非易失性存储器单元中的时间段内，子开关断开，从而间歇地停止对数据处理装置的电力供应。
-
公开(公告)号：US12205965B2
公开(公告)日：2025-01-21
申请号：US18231871
申请日：2023-08-09
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Takayuki Ikeda , Yoshiyuki Kurokawa , Shintaro Harada , Hidetomo Kobayashi , Roh Yamamoto , Kiyotaka Kimura , Takashi Nakagawa , Yusuke Negoro
IPC: H01L27/146 , H01L27/12 , H01L29/786 , H04N25/40 , H04N25/766 , H04N25/77
Abstract: An imaging device capable of image processing is provided. The imaging device can retain analog data (image data) obtained by an image-capturing operation in a pixel and perform a product-sum operation of the analog data and a predetermined weight coefficient in the pixel to convert the data into binary data. When the binary data is taken in a neural network or the like, processing such as image recognition can be performed. Since enormous volumes of image data can be retained in pixels in the state of analog data, processing can be performed efficiently.
-
公开(公告)号：US10452218B2
公开(公告)日：2019-10-22
申请号：US15870141
申请日：2018-01-12
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Roh Yamamoto , Hideki Uochi
IPC: G06F3/044 , G09G3/36 , G09G3/20 , H01L29/786
Abstract: A display device with less power consumption. The display device operates in a still image display period and a moving image display period, and includes a receiving circuit having a function of receiving an image signal, a driver circuit having a function of driving a display portion, and the display portion having a function of displaying an image. The display portion displays an image at a frame frequency of less than or equal to 1 Hz in the still image display period. The receiving circuit stops receiving an image signal in the still image display period. Switching from the still image display period to the moving image display period is accurately performed by an external signal.
-
公开(公告)号：US09830997B2
公开(公告)日：2017-11-28
申请号：US14976204
申请日：2015-12-21
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Roh Yamamoto
CPC classification number: G11C19/28 , G09G3/3266 , G09G2300/0452 , G09G2310/0286 , G09G2320/0233 , G09G2320/0252 , G09G2330/021
Abstract: A semiconductor device and the like with low power consumption can be provided. A shift register in which a plurality of register circuits are connected to each other in series. The plurality of register circuits each include a flip-flop circuit. An operation of the flip-flop circuit of the register circuit in one stage is determined by a clock signal, an output signal of the register circuit in the previous stage, an output signal of the register circuit in the one stage, and an output signal of the register circuit in the next stage. Data stored in the flip-flop circuits in the register circuits in stages that are two or more stages before the one stage and in the register circuits in stages that are two or more stages after the one stage are not rewritten.
-
Patent Agency Ranking
公开(公告)号：US20210384239A1
公开(公告)日：2021-12-09
申请号：US17403911
申请日：2021-08-17
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Takayuki Ikeda , Yoshiyuki Kurokawa , Shintaro Harada , Hidetomo Kobayashi , Roh Yamamoto , Kiyotaka Kimura , Takashi Nakagawa , Yusuke Negoro
IPC: H01L27/146 , H01L27/12 , H01L29/786 , H04N5/341 , H04N5/374 , H04N5/3745
Abstract: An imaging device capable of image processing is provided. The imaging device can retain analog data (image data) obtained by an image-capturing operation in a pixel and perform a product-sum operation of the analog data and a predetermined weight coefficient in the pixel to convert the data into binary data. When the binary data is taken in a neural network or the like, processing such as image recognition can be performed. Since enormous volumes of image data can be retained in pixels in the state of analog data, processing can be performed efficiently.
-
公开(公告)号：US11101302B2
公开(公告)日：2021-08-24
申请号：US16615156
申请日：2018-05-16
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Takayuki Ikeda , Yoshiyuki Kurokawa , Shintaro Harada , Hidetomo Kobayashi , Roh Yamamoto , Kiyotaka Kimura , Takashi Nakagawa , Yusuke Negoro
IPC: H01L27/146 , H01L27/12 , H01L29/786 , H04N5/341 , H04N5/374 , H04N5/3745
Abstract: An imaging device capable of image processing is provided.
The imaging device can retain analog data (image data) obtained by an image-capturing operation in a pixel and perform a product-sum operation of the analog data and a predetermined weight coefficient in the pixel to convert the data into binary data. When the binary data is taken in a neural network or the like, processing such as image recognition can be performed. Since enormous volumes of image data can be retained in pixels in the state of analog data, processing can be performed efficiently.-
公开(公告)号：US10224906B2
公开(公告)日：2019-03-05
申请号：US15438861
申请日：2017-02-22
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Roh Yamamoto
IPC: H03K3/0233 , H03K3/3565 , H03K5/24
Abstract: A hysteresis comparator that has a small circuit area and low power consumption is provided. A differential pair in the comparator is formed using transistors each including a back gate. The comparator is configured to apply an inverted signal of a logic value of an output signal of the comparator to the back gate of the transistor. That is, the threshold voltage of the transistor is controlled by the inverted signal. By the change of the threshold voltage, hysteresis can be added to an input comparison voltage.
-
公开(公告)号：US09041442B2
公开(公告)日：2015-05-26
申请号：US13888454
申请日：2013-05-07
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Roh Yamamoto , Kazunori Watanabe
CPC classification number: H03F3/45076 , G06G7/186 , H03F2203/45116 , H03F2203/45332 , H03K17/002
Abstract: A semiconductor device including an integrator circuit, in which electric discharge from a capacitor can be reduced to shorten time required for charging the capacitor in the case where supply of power supply voltage is stopped and restarted, and a method for driving the semiconductor device are provided. One embodiment has a structure in which a transistor with small off-state current is electrically connected in series to a capacitor in an integrator circuit. Further, in one embodiment of the present invention, a transistor with small off-state current is electrically connected in series to a capacitor in an integrator circuit; the transistor is on in a period during which power supply voltage is supplied; and the transistor is off in a period during which supply of the power supply voltage is stopped.
Abstract translation: 一种包括积分电路的半导体器件，其中可以减少来自电容器的放电，以缩短在停止并重新启动电源电压的情况下为电容器充电所需的时间，以及驱动该半导体器件的方法 。 一个实施例具有其中具有小截止电流的晶体管与积分电路中的电容器串联电连接的结构。 此外，在本发明的一个实施例中，具有小截止电流的晶体管与积分电路中的电容器串联电连接; 在提供电源电压的期间，晶体管导通; 在停止供电电压的期间，晶体管截止。
-
10.发明申请SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE 有权用于驱动半导体器件的半导体器件和方法以及电子器件公开(公告)号：US20130272055A1
公开(公告)日：2013-10-17
申请号：US13803602
申请日：2013-03-14
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Roh Yamamoto
IPC: G11C11/24
CPC classification number: G11C11/24 , G11C11/403 , G11C11/405 , H01L27/115 , H01L27/1156
Abstract: The memory circuit has a first writing mode in which data can be retained for a long time and a second writing mode in which data can be written at high speed. The memory circuit in which data reading is performed on the basis of a determined conductive state of a transistor includes first and second capacitor parts that are connected through a switch and retain electric charge corresponding to the data. The first writing mode is a mode where the switch is on and electric charge corresponding to the data is accumulated in the first and second capacitor parts that are electrically connected. The second writing mode is a mode where the switch is off, electric charge corresponding to the data is accumulated in the first capacitor part, and electric charge corresponding to the data is not accumulated in the second capacitor part.
Abstract translation: 存储器电路具有第一写入模式，其中数据可以长时间保持，并且第二写入模式可以高速写入数据。 基于晶体管的确定的导通状态执行数据读取的存储电路包括通过开关连接并保持与数据相对应的电荷的第一和第二电容器部分。 第一写入模式是开关导通的模式，并且与数据对应的电荷被累积在电连接的第一和第二电容器部分中。 第二写入模式是开关关闭的模式，对应于数据的电荷被累积在第一电容器部分中，并且与数据相对应的电荷没有积累在第二电容器部分中。
-
-
-
-
-
-
-
-
-
Search Results
25
records
(took 0.025 seconds)
