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13 条记录 (耗时 0.019 秒)

    Neural network semiconductor device and system using the same
    1.
    发明授权
    Neural network semiconductor device and system using the same 有权

    公开(公告)号：US11755286B2

    公开(公告)日：2023-09-12

    申请号：US17359859

    申请日：2021-06-28

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Shintaro Harada ,  Yoshiyuki Kurokawa ,  Takeshi Aoki

    IPC分类号： G06F7/544 ,  G06N3/065 ,  H01L29/786 ,  G06N3/04

    CPC分类号： G06F7/5443 ,  G06N3/04 ,  G06N3/065 ,  H01L29/7869

    摘要： A semiconductor device capable of performing product-sum operation is provided. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. The semiconductor device retains first analog data and reference analog data in the first memory cell and the second memory cell, respectively. A potential corresponding to second analog data is applied to each of them as a selection signal, whereby current depending on the sum of products of the first analog data and the second analog data is obtained. The offset circuit includes a constant current circuit comprising a transistor and a capacitor. A first terminal of the transistor is electrically connected to a first gate of the transistor and a first terminal of the capacitor. A second gate of the transistor is electrically connected to a second terminal of the capacitor. A voltage between the first terminal and the second gate of the transistor is held in the capacitor, whereby a change in source-drain current of the transistor can be suppressed.

    Semiconductor neural network device including a synapse circuit comprising memory cells and an activation function circuit
    3.
    发明授权
    Semiconductor neural network device including a synapse circuit comprising memory cells and an activation function circuit 有权

    公开(公告)号：US11556771B2

    公开(公告)日：2023-01-17

    申请号：US16603710

    申请日：2018-04-02

    申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    发明人： Shintaro Harada ,  Hiroki Inoue ,  Takeshi Aoki

    IPC分类号： G11C11/40 ,  G11C11/54 ,  G11C7/10 ,  G06N3/063

    摘要： Novel connection between neurons of a neural network is provided.
    A perceptron included in the neural network includes a plurality of neurons; the neuron includes a synapse circuit and an activation function circuit; and the synapse circuit includes a plurality of memory cells. A bit line selected by address information for selecting a memory cell is shared by a plurality of perceptrons. The memory cell is supplied with a weight coefficient of an analog signal, and the synapse circuit is supplied with an input signal. The memory cell multiplies the input signal by the weight coefficient and converts the multiplied result into a first current. The synapse circuit generates a second current by adding a plurality of first currents and converts the second current into a first potential. The activation function circuit is a semiconductor device that converts the first potential into a second potential by a ramp function and supplies the second potential as an input signal of the synapse circuit included in the perceptron in a next stage.

    Electronic device
    4.
    发明授权
    Electronic device 有权

    公开(公告)号：US11139298B2

    公开(公告)日：2021-10-05

    申请号：US16638799

    申请日：2018-08-27

    申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    发明人： Shintaro Harada ,  Tatsunori Inoue ,  Yoshiyuki Kurokawa ,  Shunpei Yamazaki

    IPC分类号： H01L27/00 ,  H01L29/00 ,  H01L27/105 ,  G06N3/063 ,  H01L27/12 ,  H01L29/786

    摘要： An electronic device including a semiconductor device capable of intermittent driving is provided. The electronic device includes a semiconductor device, and the semiconductor device includes a current mirror circuit, a bias circuit, and first to third transistors. The current mirror circuit includes a first output terminal and a second output terminal, and the current mirror circuit is electrically connected to a power supply line through the first transistor. The current mirror circuit has a function of outputting current corresponding to a potential of the first output terminal from the first output terminal and the second output terminal. The bias circuit includes a current source circuit and a current sink circuit, the current source circuit is electrically connected to the second output terminal through the second transistor, and the current sink circuit is electrically connected to the second output terminal through the third transistor. Switching on/off states of the first to third transistors achieves intermittent driving of the semiconductor device.

    Semiconductor device having neural network
    6.
    发明授权
    Semiconductor device having neural network 有权

    公开(公告)号：US11568224B2

    公开(公告)日：2023-01-31

    申请号：US16621305

    申请日：2018-06-11

    申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    发明人： Yoshiyuki Kurokawa ,  Shintaro Harada

    IPC分类号： G06N3/063 ,  G06F7/544 ,  G06F9/30

    摘要： A semiconductor device capable of efficiently recognizing images utilizing a neural network is provided. The semiconductor device includes a shift register group, a D/A converter, and a product-sum operation circuit. The product-sum operation circuit includes an analog memory and stores a parameter of a filter. The shift register group captures image data and outputs part of the image data to the D/A converter while shifting the image data. The D/A converter converts the part of the input image data into analog data and outputs the analog data to the product-sum operation circuit.

    Logic circuit formed using unipolar transistor, and semiconductor device
    8.
    发明授权
    Logic circuit formed using unipolar transistor, and semiconductor device 有权

    公开(公告)号：US12040795B2

    公开(公告)日：2024-07-16

    申请号：US17413791

    申请日：2019-12-10

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Hiroki Inoue ,  Munehiro Kozuma ,  Takeshi Aoki ,  Shuji Fukai ,  Fumika Akasawa ,  Shintaro Harada ,  Sho Nagao

    IPC分类号： H03K19/094 ,  H01L27/06

    CPC分类号： H03K19/094 ,  H01L27/0629

    摘要： A semiconductor device using unipolar transistors, in which high and low levels are expressed using high and low power supply potentials, is provided. The semiconductor device includes four transistors, two capacitors, two wirings, two input terminals, and an output terminal. A source or a drain of the first transistor and a source or a drain of the fourth transistor are electrically connected to the first wiring. A gate of the fourth transistor is electrically connected to the first input terminal, and a gate of the second transistor is electrically connected to the second input terminal. A source or a drain of the second transistor and a source or a drain of the third transistor are electrically connected to the second wiring. The first transistor, the second transistor, and the two capacitors are electrically connected to the output terminal.

    Detecting device and semiconductor device
    9.
    发明授权
    Detecting device and semiconductor device 有权

    公开(公告)号：US11909397B2

    公开(公告)日：2024-02-20

    申请号：US17286091

    申请日：2019-10-17

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Shintaro Harada ,  Takayuki Ikeda

    IPC分类号： H02J7/00 ,  H03K3/037 ,  G01R31/3835 ,  G01R31/36 ,  G06F1/06

    CPC分类号： H03K3/037 ,  G01R31/3644 ,  G01R31/3835 ,  G06F1/06

    摘要： The power of a semiconductor device is reduced. The semiconductor device includes a latch circuit composed of a dynamic circuit. The latch circuit includes a first circuit having a decoding function, a plurality of capacitors, a plurality of clock input terminals, a signal input terminal, a first output terminal, and a second output terminal. In a period during which “H” is supplied to a first clock signal, the potential of the first capacitor is updated on the basis of the results of decoding performed by the first circuit. In a period during which “H” is supplied to a second clock signal, the potential of the second capacitor is updated on the basis of the potential of the first capacitor, and the potential of the second capacitor is supplied as a first output signal to the first output terminal. In a period during which “H” is supplied to a third clock signal, the potential of the third capacitor is updated on the basis of the potential of the second capacitor, and the potential of the third capacitor is supplied as a second output signal to the second output terminal.