公开(公告)号：US08471581B2

公开(公告)日：2013-06-25

申请号：US12710937

申请日：2010-02-23

申请人： Seung Seoup Lee ,  Soon Gyu Yim ,  In Kyung Park

发明人： Seung Seoup Lee ,  Soon Gyu Yim ,  In Kyung Park

IPC分类号： G01R31/00

CPC分类号： G01R31/312

摘要： Disclosed herein is an apparatus and method for inspecting defects in the circuit pattern of a substrate. The apparatus for inspecting defects in a circuit pattern of a substrate includes a pin probe configured to input a voltage while coming into contact with an inspection target circuit pattern of a substrate. A capacitor sensor is provided with a membrane electrode which is opposite a connection circuit pattern to be electrically connected to the inspection target circuit pattern in a non-contact manner, and is configured to detect both capacitance and capacitance variation, generated due to displacement of the membrane electrode attributable to electrostatic attractive force acting from the connection circuit pattern on the membrane electrode. A capacitance measurement unit is connected to the capacitor sensor and is configured to measure capacitance attributable to the displacement of the membrane electrode, which is input from the capacitor sensor.

摘要翻译： 本文公开了一种用于检查衬底的电路图案中的缺陷的装置和方法。 用于检查基板的电路图案中的缺陷的装置包括：引脚探针，其被配置为在与基板的检查对象电路图案接触的同时输入电压。 电容器传感器设置有与非接触式电连接到检查对象电路图案的连接电路图案相对的膜电极，并且被配置为检测由于位移而产生的电容和电容变化 膜电极归因于从膜电极上的连接电路图案作用的静电吸引力。 电容测量单元连接到电容器传感器，并且被配置为测量归因于从电容器传感器输入的膜电极的位移的电容。

公开(公告)号：US20110115516A1

公开(公告)日：2011-05-19

申请号：US12710937

申请日：2010-02-23

申请人： Seung Seoup Lee ,  Soon Gyu Yim ,  In Kyung Park

发明人： Seung Seoup Lee ,  Soon Gyu Yim ,  In Kyung Park

IPC分类号： G01R31/02

CPC分类号： G01R31/312

摘要： Disclosed herein is an apparatus and method for inspecting defects in the circuit pattern of a substrate. The apparatus for inspecting defects in a circuit pattern of a substrate includes a pin probe configured to input a voltage while coming into contact with an inspection target circuit pattern of a substrate. A capacitor sensor is provided with a membrane electrode which is opposite a connection circuit pattern to be electrically connected to the inspection target circuit pattern in a non-contact manner, and is configured to detect both capacitance and capacitance variation, generated due to displacement of the membrane electrode attributable to electrostatic attractive force acting from the connection circuit pattern on the membrane electrode. A capacitance measurement unit is connected to the capacitor sensor and is configured to measure capacitance attributable to the displacement of the membrane electrode, which is input from the capacitor sensor.

摘要翻译： 本文公开了一种用于检查衬底的电路图案中的缺陷的装置和方法。 用于检查基板的电路图案中的缺陷的装置包括：引脚探针，其被配置为在与基板的检查对象电路图案接触的同时输入电压。 电容器传感器设置有与非接触式电连接到检查对象电路图案的连接电路图案相对的膜电极，并且被配置为检测由于位移而产生的电容和电容变化 膜电极归因于从膜电极上的连接电路图案作用的静电吸引力。 电容测量单元连接到电容器传感器，并且被配置为测量归因于从电容器传感器输入的膜电极的位移的电容。

公开(公告)号：US08378452B2

公开(公告)日：2013-02-19

申请号：US12770614

申请日：2010-04-29

申请人： Seung Seoup Lee ,  Soon Gyu Yim

发明人： Seung Seoup Lee ,  Soon Gyu Yim

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/60 ,  H01L23/3114 ,  H01L23/5223 ,  H01L28/90 ,  H01L2224/131 ,  H01L2924/01002 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/014

摘要： Disclosed is a wafer level package having a cylindrical capacitor, which is capable of increasing electrostatic capacity thanks to the use of a cylindrical capacitor structure and which includes a wafer chip having a bonding pad formed thereon and an insulating layer formed thereon and exposing the bonding pad, a redistribution layer connected to the bonding pad and extending to one side of the insulating layer, a cylindrical outer electrode connected to the redistribution layer and having a center opening therein, a cylindrical inner electrode formed in the center opening of the outer electrode so as to be separated from the outer electrode, a dielectric layer formed between the outer electrode and the inner electrode, and a resin sealing portion formed on the insulating layer to cover the redistribution layer, the inner electrode, the outer electrode and the dielectric layer and having a first recess for exposing an upper surface of the inner electrode. A method of fabricating the wafer level package having a cylindrical capacitor is also provided.

公开(公告)号：US08656582B2

公开(公告)日：2014-02-25

申请号：US12424494

申请日：2009-04-15

申请人： Seung Seoup Lee ,  Soon Gyu Yim ,  Jong Woo Han

发明人： Seung Seoup Lee ,  Soon Gyu Yim ,  Jong Woo Han

IPC分类号： H05K3/30 ,  H01L21/00

CPC分类号： H01L24/95 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/83193 ,  H01L2224/838 ,  H01L2224/95085 ,  H01L2224/95146 ,  H01L2224/95147 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  Y10T29/4913 ,  Y10T156/10 ,  H01L2924/00

摘要： Disclosed herein are a method of attaching a die using a self-assembling monolayer and a package substrate including a die attached thereto using a self-assembling monolayer. A first self-assembling monolayer formed on a die and a second self-assembling monolayer formed on a substrate are provided with the same hydrophilic or hydrophobic functional group, so that the die is attached to the substrate using an attractive force acting between the first and second self-assembling monolayers. An accuracy of alignment between the die and the substrate can be improved by the simple solution.

摘要翻译： 本文公开了一种使用自组装单层和包含基片的封装衬底附接裸片的方法，所述封装衬底使用自组装单层附着于其上。 在模具上形成的第一自组装单层和在基底上形成的第二自组装单层设置有相同的亲水或疏水官能团，使得模具使用在第一和第 第二自组装单层。 可以通过简单的解决方案来改善管芯和衬底之间的对准精度。

公开(公告)号：US20100187002A1

公开(公告)日：2010-07-29

申请号：US12424494

申请日：2009-04-15

申请人： Seung Seoup Lee ,  Soon Gyu Yim ,  Jong Woo Han

发明人： Seung Seoup Lee ,  Soon Gyu Yim ,  Jong Woo Han

IPC分类号： H05K1/16 ,  B29C65/00

CPC分类号： H01L24/95 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/83193 ,  H01L2224/838 ,  H01L2224/95085 ,  H01L2224/95146 ,  H01L2224/95147 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  Y10T29/4913 ,  Y10T156/10 ,  H01L2924/00

摘要： Disclosed herein are a method of attaching a die using a self-assembling monolayer and a package substrate including a die attached thereto using a self-assembling monolayer. A first self-assembling monolayer formed on a die and a second self-assembling monolayer formed on a substrate are provided with the same hydrophilic or hydrophobic functional group, so that the die is attached to the substrate using an attractive force acting between the first and second self-assembling monolayers. An accuracy of alignment between the die and the substrate can be improved by the simple solution.

摘要翻译： 本文公开了一种使用自组装单层和包含基片的封装衬底附接裸片的方法，所述封装衬底使用自组装单层附着于其上。 在模具上形成的第一自组装单层和在基底上形成的第二自组装单层设置有相同的亲水或疏水官能团，使得模具使用在第一和第 第二自组装单层。 可以通过简单的解决方案来改善管芯和衬底之间的对准精度。

公开(公告)号：US20130147014A1

公开(公告)日：2013-06-13

申请号：US13752238

申请日：2013-01-28

申请人： Seung Seoup Lee ,  Soon Gyu Yim

发明人： Seung Seoup Lee ,  Soon Gyu Yim

IPC分类号： H01L49/02

CPC分类号： H01L28/60 ,  H01L23/3114 ,  H01L23/5223 ,  H01L28/90 ,  H01L2224/131 ,  H01L2924/01002 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/014

摘要： Disclosed is a wafer level package having a cylindrical capacitor, which is capable of increasing electrostatic capacity thanks to the use of a cylindrical capacitor structure and which includes a wafer chip having a bonding pad formed thereon and an insulating layer formed thereon and exposing the bonding pad, a redistribution layer connected to the bonding pad and extending to one side of the insulating layer, a cylindrical outer electrode connected to the redistribution layer and having a center opening therein, a cylindrical inner electrode formed in the center opening of the outer electrode so as to be separated from the outer electrode, a dielectric layer formed between the outer electrode and the inner electrode, and a resin sealing portion formed on the insulating layer to cover the redistribution layer, the inner electrode, the outer electrode and the dielectric layer and having a first recess for exposing an upper surface of the inner electrode. A method of fabricating the wafer level package having a cylindrical capacitor is also provided.

摘要翻译： 公开了一种具有圆柱形电容器的晶片级封装，其由于使用圆柱形电容器结构而能够增加静电容量，并且其包括其上形成有焊盘的晶片芯片和形成在其上的绝缘层，并露出焊盘 连接到接合焊盘并延伸到绝缘层的一侧的再分配层，连接到再分布层并且具有中心开口的圆筒形外部电极，形成在外部电极的中心开口中的圆柱形内部电极，以便 与外部电极分离，形成在外部电极和内部电极之间的电介质层和形成在绝缘层上以覆盖再分配层，内部电极，外部电极和电介质层的树脂密封部分，并且具有 用于暴露内部电极的上表面的第一凹部。 还提供了一种制造具有圆柱形电容器的晶片级封装的方法。

公开(公告)号：US08410465B2

公开(公告)日：2013-04-02

申请号：US12716948

申请日：2010-03-03

申请人： Seung Seoup Lee ,  Jae Cheon Doh ,  In Kyung Park

发明人： Seung Seoup Lee ,  Jae Cheon Doh ,  In Kyung Park

IPC分类号： G01N21/86

CPC分类号： G01R31/309

摘要： An apparatus for inspecting defects in a circuit pattern is described. The apparatus includes at least one laser unit for radiating a laser beam onto a first end of a circuit pattern formed on a substrate. The apparatus also includes a capacitor sensor disposed opposite a second end of the circuit pattern, which is connected to the first end of the circuit pattern through a via hole, in a non-contact manner. The apparatus also includes a voltage source connected to the capacitor sensor and configured to apply a voltage. The apparatus also includes a measurement unit connected to the capacitor sensor and configured to detect variation in impedance generated in the capacitor sensor.

摘要翻译： 描述了用于检查电路图案中的缺陷的装置。 该装置包括用于将激光束照射到形成在基板上的电路图案的第一端上的至少一个激光单元。 该装置还包括电容传感器，该电容器传感器与电路图案的第二端相对设置，其以非接触方式通过通孔连接到电路图案的第一端。 该装置还包括连接到电容器传感器并被配置为施加电压的电压源。 该装置还包括连接到电容器传感器并被配置为检测在电容器传感器中产生的阻抗变化的测量单元。

公开(公告)号：US20110109339A1

公开(公告)日：2011-05-12

申请号：US12710149

申请日：2010-02-22

申请人： Seung Seoup Lee

发明人： Seung Seoup Lee

IPC分类号： G01R31/02 ,  G01R31/26 ,  G06K9/00

CPC分类号： G01R31/308 ,  G01N27/84 ,  G01R1/06783

摘要： Disclosed herein is an apparatus and method for inspecting a circuit of a substrate. The apparatus includes a pin probe coming into contact with a first end of an electrode formed on a first side of a substrate, a voltage source for applying a voltage to the pin probe, a film disposed at a second end of the electrode formed on a second side of the substrate, a dielectric fluid sealed in the film, and an electronic ink dispersed in the dielectric fluid, and charged with electricity to flow when the electrode is electrified. The present invention is advantageous in that whether an electrode has been electrified is measured using charged electronic ink, so that the use of a pin probe is limited to one side of a substrate, thus reducing cost required for the entire inspection.

摘要翻译： 本文公开了一种用于检查基板的电路的装置和方法。 该装置包括与形成在基板的第一侧上的电极的第一端接触的引脚探针，用于向引脚探针施加电压的电压源，设置在电极形成的电极的第二端的膜 衬底的第二面，密封在膜中的电介质流体和分散在电介质流体中的电子墨水，并且当电极通电时，电荷被带电流动。 本发明的优点在于，使用带电电子墨水来测量电极是否通电，使得针式探头的使用限于基板的一侧，从而降低了整个检查所需的成本。

公开(公告)号：US20100052164A1

公开(公告)日：2010-03-04

申请号：US12289702

申请日：2008-10-31

申请人： Seung Seoup Lee ,  Sung Yi

发明人： Seung Seoup Lee ,  Sung Yi

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L23/3114 ,  H01L21/76804 ,  H01L21/76817 ,  H01L21/76885 ,  H01L24/02 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/181 ,  H01L2924/00

摘要： The present invention relates to a wafer level package and a method of manufacturing the same and provides a wafer level package structure including a wafer having a die pad; a redistribution line formed to be connected on a top surface of the die pad; a metal post connected to a top surface of the redistribution line and formed in a flexure hinge structure; and a molding resin formed between the metal posts.

摘要翻译： 本发明涉及一种晶片级封装及其制造方法，提供一种晶片级封装结构，其包括具有管芯焊盘的晶片; 形成为连接在所述管芯焊盘的上表面上的再分配线; 连接到再分配线的顶表面并形成在弯曲铰链结构中的金属柱; 以及形成在金属柱之间的模制树脂。

公开(公告)号：US08624618B2

公开(公告)日：2014-01-07

申请号：US12710149

申请日：2010-02-22

申请人： Seung Seoup Lee

发明人： Seung Seoup Lee

IPC分类号： G01R31/00

CPC分类号： G01R31/308 ,  G01N27/84 ,  G01R1/06783

摘要： An apparatus and method for inspecting a circuit of a substrate is described. The apparatus includes a pin probe coming into contact with a first end of an electrode formed on a first side of a substrate, a voltage source for applying a voltage to the pin probe, a film disposed at a second end of the electrode formed on a second side of the substrate, a dielectric fluid sealed in the film, and an electronic ink dispersed in the dielectric fluid, and charged with electricity to flow when the electrode is electrified. The present invention is advantageous in that whether an electrode has been electrified is measured using charged electronic ink, so that the use of a pin probe is limited to one side of a substrate, thus reducing cost required for the entire inspection.

摘要翻译： 描述了用于检查基板的电路的装置和方法。 该装置包括与形成在基板的第一侧上的电极的第一端接触的引脚探针，用于向引脚探针施加电压的电压源，设置在电极形成的电极的第二端的膜 衬底的第二面，密封在膜中的电介质流体和分散在电介质流体中的电子墨水，并且当电极通电时，电荷被带电流动。 本发明的优点在于，使用带电电子墨水来测量电极是否通电，使得针式探头的使用限于基板的一侧，从而降低了整个检查所需的成本。