公开(公告)号：US09773560B2

公开(公告)日：2017-09-26

申请号：US14964056

申请日：2015-12-09

申请人： Jong-Chul Park ,  Seung-Bum Kim ,  Myung-Hoon Choi

发明人： Jong-Chul Park ,  Seung-Bum Kim ,  Myung-Hoon Choi

IPC分类号： G11C16/08 ,  G11C16/14 ,  G11C16/34 ,  G11C16/10 ,  G11C16/16

CPC分类号： G11C16/14 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3477

摘要： A nonvolatile memory device includes a memory cell array having memory cells, a row decoder circuit connected to the memory cells through word lines, a page buffer circuit connected to the memory cells through bit lines, and a control circuit controlling the row decoder circuit and the page buffer circuit to repeatedly perform an erase loop including an erase and an erase verification with respect to the memory cells. The control circuit is configured to select one of an increase and a decrease of an erase voltage according to a result of the erase verification of a current erase loop and apply the controlled erase voltage to the memory cells in the erase operation of a subsequent erase loop.

公开(公告)号：US08654580B2

公开(公告)日：2014-02-18

申请号：US13316636

申请日：2011-12-12

申请人： Dong Ku Kang ,  Seung-Bum Kim ,  Tae-Young Kim ,  Sun-Jun Park

发明人： Dong Ku Kang ,  Seung-Bum Kim ,  Tae-Young Kim ,  Sun-Jun Park

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/16

摘要： A method is for programming a memory block of a non-volatile memory device. The non-volatile memory device is operatively connected to a memory controller, and the memory block defined by a plurality of word lines located between a string select line and a common source line corresponding to the string select line. The method includes programming a first sub-block of the memory block, determining in the non-volatile memory device when a reference word line is programmed during programming of the first sub-block, and partial erasing a second sub-block of the memory block upon determining that the reference word line is programmed during programming of the first sub-block.

摘要翻译： 一种用于编程非易失性存储器件的存储器块的方法。 非易失性存储器件可操作地连接到存储器控制器，并且由位于串选择线和对应于字符串选择行的公共源线之间的多个字线定义的存储器块。 该方法包括对存储块的第一子块进行编程，在第一子块的编程期间对参考字线进行编程以及部分擦除存储块的第二子块时，确定非易失性存储器件 一旦确定在第一子块的编程期间编程了参考字线。

公开(公告)号：US08582365B2

公开(公告)日：2013-11-12

申请号：US13032855

申请日：2011-02-23

申请人： Seung-Bum Kim

发明人： Seung-Bum Kim

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/0483

摘要： Within a non-volatile memory device, a read operation directed to a nonvolatile memory cell having a positive threshold voltage applies a positive read voltage to a selected word line and a first control signal to a page buffer connected to a selected bit line, but if the memory cell has a negative threshold voltage the read operation applies a negative read voltage to the selected word line and a second control signal to the page buffer different from the first control signal.

摘要翻译： 在非易失性存储器件中，针对具有正阈值电压的非易失性存储单元的读取操作将正读取电压施加到所选字线和第一控制信号到连接到所选位线的页缓冲器，但如果 存储单元具有负的阈值电压，读取操作将一个负的读取电压施加到所选择的字线，并且将第二个控制信号施加到与第一个控制信号不同的页面缓冲器。

公开(公告)号：US07937044B2

公开(公告)日：2011-05-03

申请号：US11965492

申请日：2007-12-27

申请人： Hee-Chan Choi ,  Seung-Bum Kim ,  Dong-Woo Lee

发明人： Hee-Chan Choi ,  Seung-Bum Kim ,  Dong-Woo Lee

IPC分类号： H04B1/38

CPC分类号： H04B1/525 ,  G06K7/0008 ,  G06K19/0701 ,  G06K19/0715

摘要： Disclosed is an apparatus and a method for improving the receive (Rx) sensitivity of a portable Radio Frequency IDentification (RFID). The portable RFID reader/writer is equipped with a variable phase shifter which is connected between an antenna and a directional coupler and then changes an impedance in the direction of the antenna in response to controlling a phase shift, a level of a reflection signal if a transmit (Tx) signal of the portable RFID reader/writer reflected by the antenna flows into an Rx path is measured, and then the phase shift of the variable phase shifter is controlled in such a manner as to minimize the measured level of the reflection signal. Therefore, calibration is implemented so that an antenna impedance changing in response to a position in which contact is made by a user's hand may have an adaptively optimal antenna reflection coefficient, thereby improving the Rx sensitivity.

摘要翻译： 公开了一种用于提高便携式射频识别（RFID）的接收（Rx）灵敏度的装置和方法。 便携式RFID阅读器/写入器配备有可变移相器，其连接在天线和定向耦合器之间，然后响应于控制相移而改变天线方向上的阻抗，反射信号的电平如果 测量由天线反射的便携式RFID读写器的发送（Tx）信号流入Rx路径，然后控制可变移相器的相移，使得反射信号的测量电平最小化 。 因此，实现校准，使得响应于由用户的手进行接触的位置而改变的天线阻抗可以具有自适应地最佳的天线反射系数，从而提高Rx灵敏度。

公开(公告)号：US20080003813A1

公开(公告)日：2008-01-03

申请号：US11641295

申请日：2006-12-18

申请人： Ki-Won Nam ,  Seung-Bum Kim

发明人： Ki-Won Nam ,  Seung-Bum Kim

IPC分类号： H01L21/44

CPC分类号： H01L21/76841 ,  H01L21/02071 ,  H01L21/32135

摘要： A method for patterning a metal line includes forming a barrier metal layer and a metal layer, etching the metal layer, etching the barrier metal layer to form a passivation layer on an etched surface of the barrier metal layer, and cleaning a resultant structure where the passivation layer is formed.

摘要翻译： 图案化金属线的方法包括形成阻挡金属层和金属层，蚀刻金属层，蚀刻阻挡金属层以在阻挡金属层的蚀刻表面上形成钝化层，以及清洗所得结构，其中 形成钝化层。

公开(公告)号：US09607700B2

公开(公告)日：2017-03-28

申请号：US15065906

申请日：2016-03-10

申请人： Seung-Bum Kim

发明人： Seung-Bum Kim

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/10 ,  G11C7/1087 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5642

摘要： The method of operating a non-volatile memory device includes dumping data stored in input latches of a page buffer to other latches of the page buffer to receive second data to be written to a second cell group of a memory cell array from outside the non-volatile memory device during writing of first data to a first cell group of the memory cell array. In the method, receiving of the second data may be finished before the writing of the first data is finished.

公开(公告)号：US20120170365A1

公开(公告)日：2012-07-05

申请号：US13316636

申请日：2011-12-12

申请人： Dong Ku Kang ,  Seung-Bum Kim ,  Tae-Young Kim ,  Sun-Jun Park

发明人： Dong Ku Kang ,  Seung-Bum Kim ,  Tae-Young Kim ,  Sun-Jun Park

IPC分类号： G11C16/16

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/16

摘要： A method is for programming a memory block of a non-volatile memory device. The non-volatile memory device is operatively connected to a memory controller, and the memory block defined by a plurality of word lines located between a string select line and a common source line corresponding to the string select line. The method includes programming a first sub-block of the memory block, determining in the non-volatile memory device when a reference word line is programmed during programming of the first sub-block, and partial erasing a second sub-block of the memory block upon determining that the reference word line is programmed during programming of the first sub-block.

摘要翻译： 一种用于编程非易失性存储器件的存储器块的方法。 非易失性存储器件可操作地连接到存储器控制器，并且由位于串选择线和对应于字符串选择行的公共源线之间的多个字线定义的存储器块。 该方法包括对存储块的第一子块进行编程，在第一子块的编程期间对参考字线进行编程以及部分擦除存储块的第二子块时，确定非易失性存储器件 一旦确定在第一子块的编程期间编程了参考字线。

公开(公告)号：US20120081957A1

公开(公告)日：2012-04-05

申请号：US13246040

申请日：2011-09-27

申请人： Seung-Bum Kim ,  Ohsuk Kwon ,  Dongku Kang ,  Tae-Young Kim ,  Jaewoo Im ,  Moosung Kim ,  Jae-Duk Yu

发明人： Seung-Bum Kim ,  Ohsuk Kwon ,  Dongku Kang ,  Tae-Young Kim ,  Jaewoo Im ,  Moosung Kim ,  Jae-Duk Yu

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/30 ,  G11C16/3436

摘要： A word line voltage generating method of a flash memory which includes generating a program voltage using a positive voltage generator; generating a plurality of negative program verification voltages corresponding to a plurality of negative data states using a negative voltage generator; and generating at least one or more program verification voltages corresponding to at least one or more states using the positive voltage generator. Generating a plurality of negative program verification voltages includes generating a first negative verification voltage; discharging an output of the negative voltage generator to become higher than the first negative verification voltage; and performing a negative charge pumping operation until an output of the negative voltage generator reaches a second negative verification voltage level.

摘要翻译： 一种闪存的字线电压产生方法，包括使用正电压发生器产生编程电压; 使用负电压发生器产生对应于多个负数据状态的多个负编程验证电压; 以及使用所述正电压发生器产生对应于至少一个或多个状态的至少一个或多个程序验证电压。 生成多个负编程验证电压包括产生第一负验证电压; 将负电压发生器的输出放电到高于第一负验证电压; 并执行负电荷泵送操作直到负电压发生器的输出达到第二负验证电压电平。

公开(公告)号：US20070128805A1

公开(公告)日：2007-06-07

申请号：US11673344

申请日：2007-02-09

申请人： Seung-Bum Kim ,  Dong-Sauk Kim ,  Jung-Taik Cheong

发明人： Seung-Bum Kim ,  Dong-Sauk Kim ,  Jung-Taik Cheong

IPC分类号： H01L21/336 ,  H01L29/94

CPC分类号： H01L21/76831 ,  H01L21/76805 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888 ,  H01L29/6656 ,  H01L29/66636

摘要： The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in lateral sides of the respective gate structures; a trench formed by etching a portion of the substrate disposed in the contact junction region with a predetermined thickness; a dopant diffusion barrier layer formed on sidewalls of the trench; and a contact plug filled into a space created between the gate structures and inside of the trench, wherein the dopant diffusion barrier layer prevents dopants within the contact plug from diffusing out.

摘要翻译： 半导体存储器件及其制造方法技术领域本发明涉及一种半导体存储器件及其制造方法。 半导体存储器件，包括：形成在衬底上的多个栅极结构; 形成在所述基板下方的接触连接区域，所述接触接合区域设置在所述各个门结构的侧面; 通过以预定厚度蚀刻设置在所述接触接合区域中的所述基板的一部分而形成的沟槽; 形成在所述沟槽的侧壁上的掺杂剂扩散阻挡层; 以及填充到栅极结构和沟槽内部之间形成的空间中的接触插塞，其中所述掺杂剂扩散阻挡层防止所述接触插塞内的掺杂物扩散。

公开(公告)号：US20070099383A1

公开(公告)日：2007-05-03

申请号：US11477866

申请日：2006-06-30

申请人： Ky-Hyun Han ,  Seung-Bum Kim

发明人： Ky-Hyun Han ,  Seung-Bum Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/66621 ,  H01L29/4236

摘要： A method for fabricating a semiconductor device includes etching a predetermined portion of a substrate to form a first recess having a bottom middle portion roundly projected and bottom edge portions tapered to have a micro-trench profile; and etching the substrate beneath the first recess to form a second recess, the second recess being rounded and being wider than the first recess.

摘要翻译： 一种用于制造半导体器件的方法，包括蚀刻衬底的预定部分以形成具有圆形突出的底部中间部分和渐缩的具有微沟槽轮廓的底部边缘部分的第一凹部; 并且在所述第一凹部下蚀刻所述基底以形成第二凹部，所述第二凹部是圆形的并且比所述第一凹部更宽。