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公开(公告)号：US08259890B2
公开(公告)日：2012-09-04
申请号：US12372741
申请日：2009-02-18
IPC分类号： H03D3/24
CPC分类号： H03L7/0893 , H03L7/087 , H03L7/093 , H03L7/183 , H03L7/1976 , H03L2207/06
摘要： A phase-locked loop circuit, including: an operating circuit for detecting a difference between a reference signal and a feedback oscillating signal to generate a detected result, and generating a first control signal according to the detected result, an auxiliary circuit for generating a second control signal that is asynchronous with the first control signal, and a controllable oscillator coupled to the operating circuit and the auxiliary circuit for generating an output oscillating signal according to the first control signal and the second control signal, wherein the feedback oscillating signal is derived from the output oscillating signal.
摘要翻译： 一种锁相环电路，包括：用于检测参考信号和反馈振荡信号之间的差以产生检测结果的操作电路，以及根据检测结果生成第一控制信号;辅助电路，用于产生第二 与第一控制信号异步的控制信号，以及耦合到操作电路和辅助电路的可控振荡器，用于根据第一控制信号和第二控制信号产生输出振荡信号，其中反馈振荡信号从 输出振荡信号。
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公开(公告)号：US08644441B2
公开(公告)日：2014-02-04
申请号：US12209485
申请日：2008-09-12
申请人： Bo-Jiun Chen , Shang-Ping Chen , Ping-Ying Wang
发明人： Bo-Jiun Chen , Shang-Ping Chen , Ping-Ying Wang
IPC分类号： H03D3/24
CPC分类号： H03L7/1976 , H03L7/081
摘要： Clock generators are provided. A phase locked loop generates an output clock, a delay line is coupled to an input of the phase locked loop, and a modulation unit integrates an input signal with a constant level to generate a modulation signal controlling the delay line, thereby modulating a phase of a first input clock of the phase locked loop, such that frequency of the output clock is locked at a desired frequency.
摘要翻译： 提供时钟发生器。 锁相环产生输出时钟，延迟线耦合到锁相环的输入端，并且调制单元将输入信号与恒定电平进行积分，以产生控制延迟线的调制信号，从而调制 锁相环的第一输入时钟，使得输出时钟的频率被锁定在期望的频率。
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公开(公告)号：US08379787B2
公开(公告)日：2013-02-19
申请号：US11940486
申请日：2007-11-15
申请人： Shang-Ping Chen , Ping-Ying Wang
发明人： Shang-Ping Chen , Ping-Ying Wang
IPC分类号： H03D3/24
CPC分类号： H03B19/00 , H03L7/081 , H03L7/1976
摘要： Spread spectrum clock generators. A phase lock loop generates an output clock according to a first input clock and a second input clock, a delay line is coupled between the first input clock and the phase lock loop. A modulation unit provides a modulation signal to control the delay line thereby modulating phase of the first input clock, such that frequency of the output clock generated by the phase lock loop varies periodically.
摘要翻译： 扩频时钟发生器。 锁相环根据第一输入时钟和第二输入时钟产生输出时钟，延迟线耦合在第一输入时钟和锁相环之间。 调制单元提供调制信号以控制延迟线，从而调制第一输入时钟的相位，使得由锁相环产生的输出时钟的频率周期性地变化。
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公开(公告)号：US20100208857A1
公开(公告)日：2010-08-19
申请号：US12372741
申请日：2009-02-18
IPC分类号： H03D3/24
CPC分类号： H03L7/0893 , H03L7/087 , H03L7/093 , H03L7/183 , H03L7/1976 , H03L2207/06
摘要： A phase-locked loop circuit, including: an operating circuit for detecting a difference between a reference signal and a feedback oscillating signal to generate a detected result, and generating a first control signal according to the detected result, an auxiliary circuit for generating a second control signal that is asynchronous with the first control signal, and a controllable oscillator coupled to the operating circuit and the auxiliary circuit for generating an output oscillating signal according to the first control signal and the second control signal, wherein the feedback oscillating signal is derived from the output oscillating signal.
摘要翻译： 一种锁相环电路，包括：用于检测参考信号和反馈振荡信号之间的差以产生检测结果的操作电路，以及根据检测结果生成第一控制信号;辅助电路，用于产生第二 与第一控制信号异步的控制信号，以及耦合到操作电路和辅助电路的可控振荡器，用于根据第一控制信号和第二控制信号产生输出振荡信号，其中反馈振荡信号从 输出振荡信号。
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公开(公告)号：US20090128201A1
公开(公告)日：2009-05-21
申请号：US12209485
申请日：2008-09-12
申请人： Bo-Jiun Chen , Shang-Ping Chen , Ping-Ying Wang
发明人： Bo-Jiun Chen , Shang-Ping Chen , Ping-Ying Wang
IPC分类号： H03L7/06
CPC分类号： H03L7/1976 , H03L7/081
摘要： Clock generators are provided. A phase locked loop generates an output clock, a delay line is coupled to an input of the phase locked loop, and a modulation unit integrates an input signal with a constant level to generate a modulation signal controlling the delay line, thereby modulating a phase of a first input clock of the phase locked loop, such that frequency of the output clock is locked at a desired frequency.
摘要翻译： 提供时钟发生器。 锁相环产生输出时钟，延迟线耦合到锁相环的输入端，并且调制单元将输入信号与恒定电平进行积分，以产生控制延迟线的调制信号，从而调制 锁相环的第一输入时钟，使得输出时钟的频率被锁定在期望的频率。
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公开(公告)号：US07333568B2
公开(公告)日：2008-02-19
申请号：US10708616
申请日：2004-03-15
申请人： Chih-Cheng Chen , Shang-Ping Chen
发明人： Chih-Cheng Chen , Shang-Ping Chen
CPC分类号： H04L25/063
摘要： A data slicer includes a comparator coupled with an input signal and a reference signal for generating a sliced signal, a waveform generator for generating a calibration signal, a pulse extension device coupled to the comparator and the waveform generator for modifying the duty cycle of the sliced signal or the calibration signal to output, a charge pump coupled between the pulse extension device and a first node for charging and discharging the first node according to the signal output from the pulse extension device, a determining circuit for adjusting the data slicer according to the level change at the first node, and a feedback device coupled between the first node and the comparator for generating the reference signal.
摘要翻译： 数据限幅器包括与输入信号和用于产生分片信号的参考信号耦合的比较器，用于产生校准信号的波形发生器，耦合到比较器的脉冲扩展装置和用于修改切片信号的占空比的波形发生器 信号或校准信号输出;电荷泵，其耦合在所述脉冲扩展装置和第一节点之间，用于根据从所述脉冲扩展装置输出的信号对所述第一节点进行充电和放电;确定电路，用于根据所述脉冲扩展装置调整所述数据限幅器 第一节点处的电平变化，以及耦合在第一节点和比较器之间用于产生参考信号的反馈装置。
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公开(公告)号：US08952718B2
公开(公告)日：2015-02-10
申请号：US13572143
申请日：2012-08-10
申请人： Yan-Bin Luo , Sheng-Ming Chang , Bo-Wei Hsieh , Ming-Shi Liou , Chih-Chien Hung , Shang-Ping Chen
发明人： Yan-Bin Luo , Sheng-Ming Chang , Bo-Wei Hsieh , Ming-Shi Liou , Chih-Chien Hung , Shang-Ping Chen
IPC分类号： H03K19/003 , H03K19/00 , G11C7/10 , G11C11/4093
CPC分类号： H03K19/0005 , G11C7/10 , G11C7/1048 , G11C7/1072 , G11C11/4093
摘要： A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.
摘要翻译： 提供了一种由控制器控制的多个存储器的终端电路。 终端电路包括多个驱动器，多个电阻器和多个电容器。 每个驱动器经由传输线耦合到存储器。 每个电阻器经由相应的传输线耦合到相应的驱动器。 每个电容器耦合在相应的电阻器和参考电压之间。 控制器经由驱动器耦合到存储器，并且当经由对应于传输线的传输线传输到存储器的逻辑“0”和逻辑“1”的数量时，控制器向一个驱动器提供特定的代码 其中一个驱动器是不平衡的，以便调整与其中一个驱动器相对应的电容器的终端电压。
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公开(公告)号：US20050074076A1
公开(公告)日：2005-04-07
申请号：US10708616
申请日：2004-03-15
申请人： Chih-Cheng Chen , Shang-Ping Chen
发明人： Chih-Cheng Chen , Shang-Ping Chen
IPC分类号： H04L25/06
CPC分类号： H04L25/063
摘要： A data slicer includes a comparator coupled with an input signal and a reference signal for generating a sliced signal, a waveform generator for generating a calibration signal, a pulse extension device coupled to the comparator and the waveform generator for modifying the duty cycle of the sliced signal or the calibration signal to output, a charge pump coupled between the pulse extension device and a first node for charging and discharging the first node according to the signal output from the pulse extension device, a determining circuit for adjusting the data slicer according to the level change at the first node, and a feedback device coupled between the first node and the comparator for generating the reference signal.
摘要翻译： 数据限幅器包括与输入信号和用于产生分片信号的参考信号耦合的比较器，用于产生校准信号的波形发生器，耦合到比较器的脉冲扩展装置和用于修改切片信号的占空比的波形发生器 信号或校准信号输出;电荷泵，其耦合在所述脉冲扩展装置和第一节点之间，用于根据从所述脉冲扩展装置输出的信号对所述第一节点进行充电和放电;确定电路，用于根据所述脉冲扩展装置调整所述数据限幅器 第一节点处的电平变化，以及耦合在第一节点和比较器之间用于产生参考信号的反馈装置。
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公开(公告)号：US09336170B2
公开(公告)日：2016-05-10
申请号：US13031616
申请日：2011-02-22
申请人： Hao-Ping Hong , Shang-Ping Chen , Ding-Shiuan Shen
发明人： Hao-Ping Hong , Shang-Ping Chen , Ding-Shiuan Shen
CPC分类号： H02J7/0052 , G06F1/266 , G06F13/385 , G06F13/4072 , G06F2213/0042 , H02J7/0045 , H02J7/0068 , H02J7/0081 , H02J2007/0062
摘要： A universal serial bus device includes: a core circuit having a first pin and a second pin, and having an input impedance looking into the core circuit from the first pin and the second pin; and a charging control circuit, coupled to the core circuit, arranged for providing a voltage source having a predetermined voltage to one of the first pin and the second pin and for providing a current source having a predetermined current to the other of the first pin and the second pin; wherein the input impedance of the core circuit is configured to make the predetermined voltage and the predetermined current substantially intact when an external charger charges a battery device of the universal serial bus device.
摘要翻译： 通用串行总线装置包括：具有第一引脚和第二引脚的核心电路，并具有从第一引脚和第二引脚看入核心电路的输入阻抗; 以及连接到所述核心电路的充电控制电路，被布置成向所述第一引脚和所述第二引脚之一提供具有预定电压的电压源，并且用于向所述第一引脚中的另一个提供具有预定电流的电流源，以及 第二针 其中，所述核心电路的输入阻抗被配置为当外部充电器对所述通用串行总线设备的电池装置充电时，使所述预定电压和所述预定电流基本上完整。
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公开(公告)号：US20110279095A1
公开(公告)日：2011-11-17
申请号：US13031616
申请日：2011-02-22
申请人： Hao-Ping Hong , Shang-Ping Chen , Ding-Shiuan Shen
发明人： Hao-Ping Hong , Shang-Ping Chen , Ding-Shiuan Shen
CPC分类号： H02J7/0052 , G06F1/266 , G06F13/385 , G06F13/4072 , G06F2213/0042 , H02J7/0045 , H02J7/0068 , H02J7/0081 , H02J2007/0062
摘要： A universal serial bus device includes: a core circuit having a first pin and a second pin, and having an input impedance looking into the core circuit from the first pin and the second pin; and a charging control circuit, coupled to the core circuit, arranged for selectively providing a voltage source to one of the first pin and the second pin; wherein the input impedance of the core circuit is configured to make the voltage source substantially intact when the voltage source is coupled to one of the first pin and the second pin.
摘要翻译： 通用串行总线装置包括：具有第一引脚和第二引脚的核心电路，并具有从第一引脚和第二引脚看入核心电路的输入阻抗; 以及连接到所述核心电路的充电控制电路，被布置为选择性地将电压源提供给所述第一引脚和所述第二引脚中的一个; 其中所述核心电路的输入阻抗被配置为当所述电压源耦合到所述第一引脚和所述第二引脚中的一个引脚时使所述电压源基本上完整。
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