公开(公告)号：US20180138594A1

公开(公告)日：2018-05-17

申请号：US15553376

申请日：2016-10-14

Applicant: Sharp Kabushiki Kaisha

Inventor： Takatoshi ORUI ,  Shigeyasu MORI ,  Makoto NAKAZAWA ,  Fumiki NAKANO ,  Kiyoshi MINOURA

IPC: H01Q3/44 ,  H01Q13/10 ,  H01L27/12 ,  H01L23/66

CPC classification number: H01Q3/44 ,  H01L23/66 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1262 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/7869 ,  H01L2223/6677 ,  H01Q3/34 ,  H01Q13/10 ,  H01Q21/0012 ,  H01Q21/064 ,  H01Q21/20 ,  H01Q21/24

Abstract: A scanned antenna (1000) is a scanned antenna including antenna elements (U) arranged together, the scanned antenna comprising: a TFT substrate including a first dielectric substrate (1), TFTs, gate bus lines, source bus lines, and patch electrodes (15); a slot substrate (201) including a second dielectric substrate (51), and a slot electrode (55) formed on a first primary surface of the second dielectric substrate; a liquid crystal layer (LC) provided between the TFT substrate and the slot substrate; and a reflective conductive plate (65) arranged so as to oppose a second primary surface of the second dielectric substrate (51) with a dielectric layer (54) interposed therebetween, the second primary surface being on an opposite side from the first primary surface. The TFT substrate (TFT substrate portion (101Cb)) includes a terminal region (TR) outside of the seal portion (73), and the gate bus lines or the source bus lines are connected to gate terminal portions or source terminal portions formed in the terminal region via a transparent conductive layer (14b) provided between the seal portion (73) and the TFT substrate.

公开(公告)号：US20200381822A1

公开(公告)日：2020-12-03

申请号：US16477576

申请日：2018-01-11

Applicant: Sharp Kabushiki Kaisha

Inventor： Takatoshi ORUI ,  Tadashi OHTAKE ,  Wataru NAKAMURA ,  Kiyoshi MINOURA ,  Kenichi KITOH

IPC: H01Q3/34 ,  H01Q13/10 ,  H01Q9/04 ,  H01Q15/14 ,  H01Q21/20 ,  H01L27/12

Abstract: A scanning antenna includes a TFT substrate including a plurality of TFTs supported by a first dielectric substrate and a plurality of patch electrodes, a slot substrate including a slot electrode supported by a second dielectric substrate, a liquid crystal layer provided between the TFT substrate and the slot substrate, and a reflective conductive plate disposed opposing the second dielectric substrate across a dielectric layer. The slot electrode includes a plurality of slots disposed corresponding to the plurality of patch electrodes, each patch electrode is connected to a drain of the corresponding TFT, the slot electrode includes Cu layers, and lower metal layers and/or an upper metal layer, and the lower metal layer and/or the upper metal layer decrease about a half or more of a tensile stress of the Cu layer.

公开(公告)号：US20180337446A1

公开(公告)日：2018-11-22

申请号：US15542488

申请日：2016-10-06

Applicant: Sharp Kabushiki Kaisha

Inventor： Makoto NAKAZAWA ,  Takatoshi ORUI ,  Shigeyasu MORI ,  Fumiki NAKANO ,  Kiyoshi MINOURA

IPC: H01Q1/38 ,  H01Q21/06 ,  H01Q21/00 ,  H01Q1/24 ,  H01L23/34 ,  H01L23/66 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01Q1/38 ,  G09G3/3614 ,  G09G3/3648 ,  H01L23/345 ,  H01L23/66 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/786 ,  H01L29/78669 ,  H01L29/7869 ,  H01L2223/6677 ,  H01Q1/241 ,  H01Q3/34 ,  H01Q3/44 ,  H01Q21/0012 ,  H01Q21/0087 ,  H01Q21/064

Abstract: A TFT substrate (101) including a plurality of antenna element regions (U) arranged on a dielectric substrate (1), the TFT substrate including a transmitting/receiving region including a plurality of antenna element regions, and a non-transmitting/receiving region located outside of the transmitting/receiving region, each of the plurality of antenna element regions (U) including: a thin film transistor (10); a first insulating layer (11) covering the thin film transistor and having a first opening (CH1) which exposes a drain electrode (7D) of the thin film transistor (10); and a patch electrode (15) formed on the first insulating layer (11) and in the first opening (CH1), and electrically connected to the drain electrode (7D) of the thin film transistor, wherein the patch electrode (15) includes a metal layer, and a thickness of the metal layer is greater than a thickness of a source electrode (7S) and the drain electrode (7D) of the thin film transistor.

公开(公告)号：US20180219097A1

公开(公告)日：2018-08-02

申请号：US15747773

申请日：2016-07-19

Applicant: Sharp Kabushiki Kaisha

Inventor： Takatoshi ORUI

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7869 ,  G02F1/134363 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2001/13685 ,  H01L21/02565 ,  H01L21/0257 ,  H01L21/02576 ,  H01L21/02631 ,  H01L27/1225 ,  H01L27/1251 ,  H01L29/66969 ,  H01L29/78675 ,  H01L29/78696

Abstract: A semiconductor device (101) includes: an oxide semiconductor layer (5) supported on a substrate (1), the oxide semiconductor layer (5) having a first principal face and a second principal face opposite to each other; and a first dielectric layer (9) disposed in contact with the first principal face of the oxide semiconductor layer (5). The oxide semiconductor layer (5) has a multilayer structure that includes a main layer (5c) containing substantially no halogen element and a first halogen element-containing oxide semiconductor layer (51) containing a halogen element, the first halogen element-containing oxide semiconductor layer (51) being interposed between the main layer (50) and the first dielectric layer (9).

公开(公告)号：US20180138593A1

公开(公告)日：2018-05-17

申请号：US15553373

申请日：2016-10-25

Applicant: Sharp Kabushiki Kaisha

Inventor： Makoto NAKAZAWA ,  Takatoshi ORUI ,  Wataru NAKAMURA ,  Tadashi OHTAKE ,  Fumiki NAKANO ,  Kiyoshi MINOURA

IPC: H01Q3/44 ,  H01Q13/10 ,  H01L27/12 ,  H01L23/66

CPC classification number: H01Q1/243 ,  G02F1/1313 ,  G02F1/13394 ,  G02F1/1362 ,  G02F1/136213 ,  G02F1/292 ,  G02F2202/42 ,  G02F2203/62 ,  H01L23/66 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1262 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/7869 ,  H01L2223/6677 ,  H01Q1/125 ,  H01Q1/364 ,  H01Q3/242 ,  H01Q3/34 ,  H01Q3/44 ,  H01Q3/46 ,  H01Q13/10 ,  H01Q13/22 ,  H01Q21/06

Abstract: A scanned antenna (1000) is a scanned antenna including antenna elements (U) arranged together, the scanned antenna including: a TFT substrate (101) including a first dielectric substrate (1), TFTs, gate bus lines, source bus lines, and patch electrodes (15); a slot substrate (201) including a second dielectric substrate (51) a slot electrode (55); a liquid crystal layer (LC) provided between the TFT substrate and the slot substrate; and a reflective conductive plate (65). The slot electrode includes slots (57) arranged so as to correspond to the patch electrodes. As seen from the normal direction to the first dielectric substrate, a plurality of spacer structures (75) provided between the TFT substrate and the slot substrate are arranged so as not to overlap with first regions (Rp1) and/or second regions (Rp2), where the first regions are regions that are within a distance of 0.3 mm from edges of the slots and the second regions are regions that are within a distance of 0.3 mm from edges of the patch electrodes.