公开(公告)号：US09053980B2

公开(公告)日：2015-06-09

申请号：US13364845

申请日：2012-02-02

Applicant: Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  Guckenberger John ,  Attila Mekis

Inventor： Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  Guckenberger John ,  Attila Mekis

IPC: H01L27/12 ,  H01L21/782 ,  H01L21/84

CPC classification number: H04B10/2575 ,  H01L21/84 ,  H01L27/1203 ,  H04B10/40

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices with at least a portion of each of the wafers bonded together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

Abstract translation: 公开了用于在CMOS工艺中单片集成光子学和电子学的方法和系统，并且可以包括在具有不同硅层厚度的两个CMOS晶片上制造光子和电子器件用于光子和电子器件，其中每个晶片的至少一部分结合在一起 其中第一CMOS晶片包括光子器件，并且第二CMOS晶片包括电子器件。 电子器件可以利用穿硅通孔耦合到光学器件。 可以使用选择性区域生长过程来制造不同的厚度。 可以使用氧注入和/或在CMOS晶片上利用CMOS沟槽氧化物来制造覆层。 硅可以利用外延横向过度生长沉积在CMOS沟槽氧化物上。 可以利用选择性背面蚀刻来制造包覆层。 可以通过在选择性蚀刻的区域上沉积金属来制造反射表面。

公开(公告)号：US20120132993A1

公开(公告)日：2012-05-31

申请号：US13364909

申请日：2012-02-02

Applicant: Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  John Guckenberger ,  Attila Mekis

Inventor： Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  John Guckenberger ,  Attila Mekis

IPC: H01L27/12 ,  H01L21/782

CPC classification number: H04B10/2575 ,  H01L21/84 ,  H01L27/1203 ,  H04B10/40

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices bonded to at least a portion of each of the wafers together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

Abstract translation: 公开了用于在CMOS工艺中单片集成光子学和电子学的方法和系统，并且可以包括在具有不同硅层厚度的两个CMOS晶片上制造光子和电子器件，用于光子和电子器件，其结合到每个晶片的至少一部分 其中第一CMOS晶片包括光子器件，并且第二CMOS晶片包括电子器件。 电子器件可以利用穿硅通孔耦合到光学器件。 可以使用选择性区域生长过程来制造不同的厚度。 可以使用氧注入和/或在CMOS晶片上利用CMOS沟槽氧化物来制造覆层。 硅可以利用外延横向过度生长沉积在CMOS沟槽氧化物上。 可以利用选择性背面蚀刻来制造包覆层。 可以通过在选择性蚀刻的区域上沉积金属来制造反射表面。

公开(公告)号：US09813152B2

公开(公告)日：2017-11-07

申请号：US12241961

申请日：2008-09-30

Applicant: Thierry Pinguet ,  Steffen Gloeckner ,  Sherif Abdalla ,  Sina Mirsaidi ,  Peter De Dobbelaere ,  Lawrence C. Gunn, III

Inventor： Thierry Pinguet ,  Steffen Gloeckner ,  Sherif Abdalla ,  Sina Mirsaidi ,  Peter De Dobbelaere ,  Lawrence C. Gunn, III

IPC: H04B10/25 ,  G02B6/122 ,  G02B6/124 ,  G02B6/43 ,  G02B6/42

CPC classification number: H04B10/25 ,  G02B6/1228 ,  G02B6/124 ,  G02B6/4214 ,  G02B6/43

Abstract: Methods and systems for optoelectronics transceivers integrated on a CMOS chip are disclosed and may include receiving optical signals from optical fibers via grating couplers on a top surface of a CMOS chip, which may include a guard ring. Photodetectors may be integrated in the CMOS chip. A CW optical signal may be received from a laser source via grating couplers, and may be modulated using optical modulators, which may be Mach-Zehnder and/or ring modulators. Circuitry in the CMOS chip may drive the optical modulators. The modulated optical signal may be communicated out of the top surface of the CMOS chip into optical fibers via grating couplers. The received optical signals may be communicated between devices via waveguides. The photodetectors may include germanium waveguide photodiodes, avalanche photodiodes, and/or heterojunction diodes. The CW optical signal may be generated using an edge-emitting and/or a vertical-cavity surface emitting semiconductor laser.

公开(公告)号：US09772460B2

公开(公告)日：2017-09-26

申请号：US13033439

申请日：2011-02-23

Applicant: Daniel Kucharski ,  John Andrew Guckenberger ,  Thierry Pinguet ,  Sherif Abdalla

Inventor： Daniel Kucharski ,  John Andrew Guckenberger ,  Thierry Pinguet ,  Sherif Abdalla

IPC: G02B6/42

CPC classification number: G02B6/4274 ,  G02B6/4286

Abstract: A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between an electronics die and an optoelectronics die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

公开(公告)号：US20110206322A1

公开(公告)日：2011-08-25

申请号：US13033439

申请日：2011-02-23

Applicant: Daniel Kucharski ,  John Andrew Guckenberger ,  Thierry Pinguet ,  Sherif Abdalla

Inventor： Daniel Kucharski ,  John Andrew Guckenberger ,  Thierry Pinguet ,  Sherif Abdalla

IPC: G02B6/26

CPC classification number: G02B6/4274 ,  G02B6/4286

Abstract: A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between an electronics die and an optoelectronics die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

Abstract translation: 公开了一种用于在光通信系统中实现半导体管芯之间的高速电接口的方法和系统，并且可以包括通过可位于Tx和Rx路径中的低阻抗点的耦合焊盘来传送电子管芯和光电子管芯之间的电信号 。 电信号可以经由一个或多个电流模式，受控阻抗和/或电容耦合接口传送。 电流模式接口可以包括在管芯上的晶体管的源极和漏极端子之间分离的共源共栅放大器级。 受控阻抗接口可以包括第一管芯上的传输线驱动器和第二管芯上的传输线。 电容耦合接口可以包括由模具上的接触焊盘形成的电容器。 耦合垫可以通过以下中的一种或多种连接：引线接合，金属柱，焊球或导电树脂。 芯片可以包括CMOS并且可以以倒装芯片配置耦合。

公开(公告)号：US09331096B2

公开(公告)日：2016-05-03

申请号：US13568406

申请日：2012-08-07

Applicant: Thierry Pinguet ,  Sherif Abdalla ,  Mark Peterson ,  Gianlorenzo Masini ,  Peter DeDobbelaere

Inventor： Thierry Pinguet ,  Sherif Abdalla ,  Mark Peterson ,  Gianlorenzo Masini ,  Peter DeDobbelaere

IPC: H04B10/00 ,  H04B10/06 ,  H01L29/06 ,  H01L31/00 ,  H01L21/311 ,  H01L27/12 ,  H01L21/84 ,  H01L27/06 ,  G02B6/12 ,  G02B6/34

CPC classification number: G02B6/428 ,  G02B6/12004 ,  G02B6/34 ,  G02B6/4295 ,  G02B2006/12107 ,  G02B2006/12123 ,  G02F1/2255 ,  G02F1/2257 ,  G02F2001/212 ,  H01L21/84 ,  H01L25/0652 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2224/73265 ,  H01L2225/06541 ,  H04B10/27

Abstract: Methods and systems for hybrid integration of optical communication systems are disclosed and may include receiving continuous wave (CW) optical signals in a silicon photonics die (SPD) from an optical source external to the SPD. The received CW optical signals may be processed based on electrical signals received from an electronics die bonded to the SPD via metal interconnects. Modulated optical signals may be received in the SPD from optical fibers coupled to the SPD. Electrical signals may be generated in the SPD based on the received modulated optical signals and communicated to the electronics die via the metal interconnects. The CW optical signals may be received from an optical source assembly coupled to the SPD and/or from one or more optical fibers coupled to the SPD. The received CW optical signals may be processed utilizing one or more optical modulators, which may comprise Mach-Zehnder interferometer modulators.

Abstract translation: 公开了用于光通信系统的混合集成的方法和系统，并且可以包括在来自SPD外部的光源的硅光子管芯（SPD）中接收连续波（CW）光信号。 接收到的CW光信号可以基于从通过金属互连结合到SPD的电子管芯接收的电信号进行处理。 可以在SPD中从耦合到SPD的光纤接收调制的光信号。 电信号可以基于接收到的调制光信号在SPD中产生，并通过金属互连传送到电子管芯。 CW光信号可以从耦合到SPD的光源组件和/或从耦合到SPD的一个或多个光纤接收。 可以使用一个或多个光学调制器来处理接收的CW光信号，该调制器可以包括马赫 - 曾德干涉仪调制器。

公开(公告)号：US08895413B2

公开(公告)日：2014-11-25

申请号：US13364909

申请日：2012-02-02

Applicant: Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  John Guckenberger ,  Attila Mekis

Inventor： Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  John Guckenberger ,  Attila Mekis

IPC: H01L27/12 ,  H01L21/782 ,  H01L21/84

CPC classification number: H04B10/2575 ,  H01L21/84 ,  H01L27/1203 ,  H04B10/40

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices bonded to at least a portion of each of the wafers together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

Abstract translation: 公开了用于在CMOS工艺中单片集成光子学和电子学的方法和系统，并且可以包括在具有不同硅层厚度的两个CMOS晶片上制造光子和电子器件，用于光子和电子器件，其结合到每个晶片的至少一部分 其中第一CMOS晶片包括光子器件，并且第二CMOS晶片包括电子器件。 电子器件可以利用穿硅通孔耦合到光学器件。 可以使用选择性区域生长过程来制造不同的厚度。 可以使用氧注入和/或在CMOS晶片上利用CMOS沟槽氧化物来制造覆层。 硅可以利用外延横向过度生长沉积在CMOS沟槽氧化物上。 可以利用选择性背面蚀刻来制造包覆层。 可以通过在选择性蚀刻的区域上沉积金属来制造反射表面。

公开(公告)号：US08877616B2

公开(公告)日：2014-11-04

申请号：US12554449

申请日：2009-09-04

Applicant: Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  John Guckenberger ,  Attila Mekis

Inventor： Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  John Guckenberger ,  Attila Mekis

IPC: H01L27/12 ,  H01L21/782 ,  H01L21/84

CPC classification number: H04B10/2575 ,  H01L21/84 ,  H01L27/1203 ,  H04B10/40

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.

Abstract translation: 公开了用于在CMOS工艺中单片集成光子学和电子学的方法和系统，并且可以包括在具有不同硅层厚度的单个CMOS晶片上制造光子和电子器件。 利用体CMOS工艺和/或利用SOI CMOS工艺的SOI晶片，可以在绝缘体上半导体（SOI）晶片上制造器件。 可以使用双重SOI工艺和/或选择性区域生长工艺来制造不同的厚度。 可以利用一个或多个氧注入和/或在CMOS晶片上利用CMOS沟槽氧化物来制造覆层。 硅可以利用外延横向过度生长沉积在CMOS沟槽氧化物上。 可以利用选择性背面蚀刻来制造包覆层。 可以通过在选择性蚀刻的区域上沉积金属来制造反射表面。 集成在CMOS晶片中的二氧化硅或硅锗可以用作蚀刻停止层。

公开(公告)号：US08238014B2

公开(公告)日：2012-08-07

申请号：US12555291

申请日：2009-09-08

Applicant: Daniel Kucharski ,  Brian Welch ,  Sherif Abdalla

Inventor： Daniel Kucharski ,  Brian Welch ,  Sherif Abdalla

IPC: G02B26/00 ,  G02F1/01 ,  G02F1/03 ,  G02F1/07

CPC classification number: H04B10/5161 ,  G02B26/06 ,  G02B26/0841 ,  G02F1/0121 ,  G02F1/225 ,  G02F1/2255 ,  G02F2001/212 ,  G02F2201/58 ,  H04B10/0795 ,  H04B10/505 ,  H04B10/5053 ,  H04B10/541

Abstract: Methods and systems for encoding multi-level pulse amplitude modulated signals using integrated optoelectronics are disclosed and may include generating a multi-level, amplitude-modulated optical signal utilizing an optical modulator driven by two or more electrical input signals. The optical modulator may include optical modulator elements coupled in series and configured into groups. The number of optical modular elements and groups may configure the number of levels in the multi-level amplitude modulated optical signal. Unit drivers may be coupled to each of the groups. The electrical input signals may be synchronized before communicating them to the unit drivers utilizing flip-flops. Phase addition may be synchronized utilizing one or more electrical delay lines. The optical modulator may be integrated on a single substrate, which may include one of: silicon, gallium arsenide, germanium, indium gallium arsenide, polymers, or indium phosphide. The optical modulator may include a Mach-Zehnder interferometer or one or more ring modulators.

Abstract translation: 公开了使用集成光电子学来编码多电平脉冲幅度调制信号的方法和系统，并且可以包括利用由两个或多个电输入信号驱动的光调制器来产生多电平调幅光信号。 光调制器可以包括串联耦合并被配置成组的光调制器元件。 光学模块元件和组的数量可以配置多电平调幅光信号中的电平数量。 单元驱动器可以耦合到每个组。 电输入信号可以在使用触发器将其传送到单元驱动器之前进行同步。 可以使用一个或多个电延迟线来使相位相加同步。 光学调制器可以集成在单个衬底上，其可以包括硅，砷化镓，锗，砷化铟镓，聚合物或磷化铟中的一种。 光调制器可以包括马赫 - 曾德尔干涉仪或一个或多个环形调制器。

公开(公告)号：US20120135566A1

公开(公告)日：2012-05-31

申请号：US13364845

申请日：2012-02-02

Applicant: Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  Guckenberger John ,  Attila Mekis

Inventor： Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  Guckenberger John ,  Attila Mekis

IPC: H01L21/50

CPC classification number: H04B10/2575 ,  H01L21/84 ,  H01L27/1203 ,  H04B10/40

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices with at least a portion of each of the wafers bonded together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

Abstract translation: 公开了用于在CMOS工艺中单片集成光子学和电子学的方法和系统，并且可以包括在具有不同硅层厚度的两个CMOS晶片上制造光子和电子器件用于光子和电子器件，其中每个晶片的至少一部分结合在一起 其中第一CMOS晶片包括光子器件，并且第二CMOS晶片包括电子器件。 电子器件可以利用穿硅通孔耦合到光学器件。 可以使用选择性区域生长过程来制造不同的厚度。 可以使用氧注入和/或在CMOS晶片上利用CMOS沟槽氧化物来制造覆层。 硅可以利用外延横向过度生长沉积在CMOS沟槽氧化物上。 可以利用选择性背面蚀刻来制造包覆层。 可以通过在选择性蚀刻的区域上沉积金属来制造反射表面。