公开(公告)号：US07576585B2

公开(公告)日：2009-08-18

申请号：US12047162

申请日：2008-03-12

申请人： Shigetaka Asano ,  Kazuyoshi Kikuta

发明人： Shigetaka Asano ,  Kazuyoshi Kikuta

IPC分类号： H03H11/26

CPC分类号： H03K5/133 ,  H03K2005/00026 ,  H03K2005/00058

摘要： A delay circuit, including: a plurality of first delay units coupled in series and each configured to generate a delay time that is approximately double a unit delay time; a second delay unit configured to generate the unit delay time and coupled to a last stage of the plurality of first delay units; and a selector configured to select either an output signal of the last stage of the plurality of first delay units or an output signal of the second delay unit, wherein an external input signal is input to the first delay unit and to each second delay unit, and the first delay unit and the second delay unit each include a switch circuit configured to output with a delay either an output signal of a previous stage delay unit or the external input signal.

摘要翻译： 一种延迟电路，包括：串联耦合的多个第一延迟单元，每个被配置为产生大约是单位延迟时间的两倍的延迟时间; 第二延迟单元，被配置为产生所述单位延迟时间并耦合到所述多个第一延迟单元的最后一级; 以及选择器，其被配置为选择所述多个第一延迟单元的最后级的输出信号或所述第二延迟单元的输出信号，其中外部输入信号被输入到所述第一延迟单元和每个第二延迟单元， 并且第一延迟单元和第二延迟单元各自包括被配置为延迟输出前级延迟单元的输出信号或外部输入信号的开关电路。

公开(公告)号：US08489910B2

公开(公告)日：2013-07-16

申请号：US12817692

申请日：2010-06-17

申请人： Shigetaka Asano

发明人： Shigetaka Asano

IPC分类号： G06F1/00 ,  G05F1/00 ,  H02M3/156 ,  H02M1/12 ,  H03K17/00 ,  G09G3/14 ,  G09G3/32 ,  F21V7/04

CPC分类号： H03K7/08

摘要： A timing controller includes a controller that controls an operation timing of a controlled unit, and a setting unit that associates a timing obtained by dividing a setting of the operation timing into a plurality of timings, each timing having an identification number, and sets the control unit so that an offset period based on the associated timing is added to the operation timing of the controlled unit.

摘要翻译： 定时控制器包括：控制器，其控制受控单元的操作定时;以及设定单元，其将通过将所述操作定时的设定除以多个定时获得的定时，每个定时具有识别号，并且设置所述控制 使得基于相关联的定时的偏移周期被添加到受控单元的操作定时。

公开(公告)号：US07777539B2

公开(公告)日：2010-08-17

申请号：US11882788

申请日：2007-08-06

申请人： Shigetaka Asano

发明人： Shigetaka Asano

IPC分类号： H03L7/06

CPC分类号： H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0891

摘要： A delay adjusting circuit including a delay part in which delay elements of n+1 (n≧2) stages are connected to each other in series, a first phase comparator for detecting whether a first edge that is a transition edge of a signal of an n−1-th stage of the delay part from a first logic level to a second logic level advances from a first reference signal edge that is a transition edge of a first reference signal from the first logic level to the second logic level, a second phase comparator for detecting whether a second edge that is a transition edge of a signal of an n+1-th stage of the delay part from the first logic level to the second logic level delays from the first reference signal edge, and a delay element adjusting part that corrects a second reference signal so that the first edge advances from the first reference signal edge in the first phase comparator and the second edge delays from the first reference signal edge in the second phase comparator, and that outputs a reference bias signal for adjusting delay times of the delay elements of the delay part.

摘要翻译： 一种延迟调整电路，包括延迟部分，其中n + 1（n≥2）级的延迟元件彼此串联连接;第一相位比较器，用于检测作为信号的过渡沿的第一边缘 从第一逻辑电平到第二逻辑电平的延迟部分的第n-1级从作为第一参考信号从第一逻辑电平到第二逻辑电平的过渡沿的第一参考信号边沿前进到第二逻辑电平，第二 相位比较器，用于检测作为延迟部分的第n + 1级的信号从第一逻辑电平到第二逻辑电平的信号的转移边缘的第二边缘是否延迟第一参考信号沿;以及延迟元件 调整部分，其校正第二参考信号，使得第一边缘从第一相位比较器中的第一参考信号边缘前进，并且第二边沿从第二相位比较器中的第一参考信号边沿延迟，并且输出参考 用于调整延迟部分的延迟元件的延迟时间的反相偏置信号。

公开(公告)号：US6061311A

公开(公告)日：2000-05-09

申请号：US991878

申请日：1997-12-16

申请人： Shigetaka Asano ,  Masaru Sawada

发明人： Shigetaka Asano ,  Masaru Sawada

IPC分类号： G06F3/06 ,  G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  G11B27/30 ,  G11B5/09

CPC分类号： G11B20/1833 ,  G11B20/1217 ,  G11B27/3027 ,  G11B2220/2562

摘要： A device for reproducing data recorded on a recording medium, such as a magnetic disk or an optical disk, includes a data reading apparatus and a data reproducing apparatus. The data reading apparatus reads sector data from the reading medium, including data, synch-byte signals and control signals, and generates a clock signal. The data reading apparatus reproduces the recorded data in accordance with the clock signal. When a synch-byte signal is detected by the reading apparatus, transmission of control signals to the reproducing apparatus is inhibited. In addition, lost data is recovered using other data and an ECC code.

摘要翻译： 用于再现记录在诸如磁盘或光盘的记录介质上的数据的装置包括数据读取装置和数据再现装置。 数据读取装置从读取介质读取包括数据，同步字节信号和控制信号的扇区数据，并产生时钟信号。 数据读取装置根据时钟信号再现记录的数据。 当读取装置检测到同步字节信号时，禁止向再现装置发送控制信号。 此外，使用其他数据和ECC代码恢复丢失的数据。

公开(公告)号：US07602593B2

公开(公告)日：2009-10-13

申请号：US11476138

申请日：2006-06-28

申请人： Shigetaka Asano

发明人： Shigetaka Asano

IPC分类号： H02H7/00

CPC分类号： G06F1/305 ,  H01G4/40 ,  H03H7/0153

摘要： A semiconductor for suppressing power supply resonance caused by the external noise and preventing fluctuation of the power supply voltage. The semiconductor device includes first and second power supply wires for supplying power supply voltages, a variable capacitor circuit connected between the first and second power supply wires, a monitor circuit for detecting the fluctuation of the power supply voltage and generating an output signal indicating the detection thereof, and a controller for changing the capacitance value of the variable capacitor circuit based on the output signal of the monitor circuit.

摘要翻译： 一种用于抑制由外部噪声引起的电源谐振并防止电源电压波动的半导体。 半导体器件包括用于提供电源电压的第一和第二电源线，连接在第一和第二电源线之间的可变电容器电路，用于检测电源电压的波动并产生指示检测的输出信号的监视电路 以及用于根据监视电路的输出信号改变可变电容电路的电容值的控制器。

公开(公告)号：US20070195483A1

公开(公告)日：2007-08-23

申请号：US11476138

申请日：2006-06-28

申请人： Shigetaka Asano

发明人： Shigetaka Asano

IPC分类号： H01G2/00

CPC分类号： G06F1/305 ,  H01G4/40 ,  H03H7/0153

摘要： A semiconductor for suppressing power supply resonance caused by the external noise and preventing fluctuation of the power supply voltage. The semiconductor device includes first and second power supply wires for supplying power supply voltages, a variable capacitor circuit connected between the first and second power supply wires, a monitor circuit for detecting the fluctuation of the power supply voltage and generating an output signal indicating the detection thereof, and a controller for changing the capacitance value of the variable capacitor circuit based on the output signal of the monitor circuit.

摘要翻译： 一种用于抑制由外部噪声引起的电源谐振并防止电源电压波动的半导体。 半导体器件包括用于提供电源电压的第一和第二电源线，连接在第一和第二电源线之间的可变电容器电路，用于检测电源电压的波动并产生指示检测的输出信号的监视电路 以及用于根据监视电路的输出信号改变可变电容电路的电容值的控制器。

公开(公告)号：US20080268555A1

公开(公告)日：2008-10-30

申请号：US12163193

申请日：2008-06-27

申请人： Shigetaka Asano

发明人： Shigetaka Asano

IPC分类号： H01L21/66

CPC分类号： H01L23/66 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P1/203 ,  H01L2924/00

摘要： An object of the invention is to provide a semiconductor device and an adjusting method for a semiconductor device wherein power source noises and noises radiated as radio waves can be reduced and power source noises inside the semiconductor device can be cut. The open stub OS1 is formed in the upper wiring layer of the semiconductor device 1. The stub length L1 is set to a length of ¼ of the wavelength of the known frequency containing peak components of noises. The noise receiving part AT1 is disposed adjacent to the open stub OS1. The open stub OS1 is connected to the power source wiring 4 by an interlayer wiring 6. The noise receiving part AT1 is biased to a ground potential. The basic wave component and odd-number harmonic waves of noises that are generated from the PLL circuit 11 and propagate (the arrow Y1 of FIG. 2) in the power source wiring 4 are reflected (arrow Y2 of FIG. 2) by the open stub OS1 so as to return to the PLL circuit 11, and do not reach the filter circuit 12.

摘要翻译： 本发明的目的是提供一种用于半导体器件的半导体器件和调整方法，其中可以减少作为无线电波辐射的电源噪声和噪声，并且可以切割半导体器件内部的电源噪声。 开放短截线OS1形成在半导体器件1的上部布线层中。短截线长度L 1被设定为包含噪声的峰值分量的已知频率的波长的1/4的长度。 噪声接收部分AT 1设置成与开路短路OS1相邻。开路短线OS1通过层间布线6连接到电源布线4.噪声接收部分AT 1被偏压到地电位。 由PLL电路11产生并传播（图2中的箭头Y 1）的基本波分量和奇数谐波在电源布线4中被反射（图2中的箭头Y 2）（图2中的箭头Y 2） 打开存根OS1，以返回到PLL电路11，并且不到达滤波电路12。

公开(公告)号：US06462686B2

公开(公告)日：2002-10-08

申请号：US09782297

申请日：2001-02-14

申请人： Shigetaka Asano ,  Yoshitaka Nakata

发明人： Shigetaka Asano ,  Yoshitaka Nakata

IPC分类号： H03M300

CPC分类号： G11B20/10009 ,  H03M1/185

摘要： A servo controller for correcting a read position of a head when reading data recorded on a recording medium. In accordance with the amplitude ratio of data signals read from each segment of a servo section defined on a recording medium, the servo controller generates an AGC signal corresponding to the next segment before reading the next segment. The data signal read from a phase detection segment of the servo section is amplified to an amplitude greater than the predetermined determination range. The amplified data signal is converted to a two-value digital signal in accordance with the determination range. The phase used during servo control is calculated in accordance with the digital signal.

摘要翻译： 一种伺服控制器，用于当读取记录在记录介质上的数据时校正磁头的读取位置。 根据从在记录介质上限定的伺服部分的每个段读取的数据信号的幅度比，伺服控制器在读取下一个段之前产生对应于下一段的AGC信号。 从伺服部分的相位检测段读取的数据信号被放大到大于预定确定范围的幅度。 放大的数据信号根据确定范围被转换为二值数字信号。 根据数字信号计算伺服控制期间使用的相位。

公开(公告)号：US08742786B2

公开(公告)日：2014-06-03

申请号：US12410157

申请日：2009-03-24

申请人： Kazufumi Komura ,  Katsumi Furukawa ,  Keiichi Fujimura ,  Takayoshi Nakamura ,  Tohru Yasuda ,  Hirohisa Nishiyama ,  Nobuyoshi Nakaya ,  Kanta Yamamoto ,  Shigetaka Asano

发明人： Kazufumi Komura ,  Katsumi Furukawa ,  Keiichi Fujimura ,  Takayoshi Nakamura ,  Tohru Yasuda ,  Hirohisa Nishiyama ,  Nobuyoshi Nakaya ,  Kanta Yamamoto ,  Shigetaka Asano

IPC分类号： G01R31/02

CPC分类号： G01R31/318555 ,  G01R31/318533 ,  G01R31/318552

摘要： A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.

摘要翻译： 一种半导体器件包括：监测器，包括耦合在第一电源线和第二电源线之间的第一元件和用于增加第一元件与第一电源线或第二电源线之间的负载值的负载;以及 确定单元，其基于所述监视器的输出来确定所述第一元素的操作状态。

公开(公告)号：US07408423B2

公开(公告)日：2008-08-05

申请号：US11136556

申请日：2005-05-25

申请人： Shigetaka Asano

发明人： Shigetaka Asano

IPC分类号： H03H11/04

CPC分类号： H01L23/66 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P1/203 ,  H01L2924/00

摘要： An object of the invention is to provide a semiconductor device and an adjusting method for a semiconductor device wherein power source noises and noises radiated as radio waves can be reduced and power source noises inside the semiconductor device can be cut. The open stub OS1 is formed in the upper wiring layer of the semiconductor device 1. The stub length L1 is set to a length of ¼ of the wavelength of the known frequency containing peak components of noises. The noise receiving part AT1 is disposed adjacent to the open stub OS1. The open stub OS1 is connected to the power source wiring 4 by an interlayer wiring 6. The noise receiving part AT1 is biased to a ground potential. The basic wave component and odd-number harmonic waves of noises that are generated from the PLL circuit 11 and propagate (the arrow Y1 of FIG. 2) in the power source wiring 4 are reflected (arrow Y2 of FIG. 2) by the open stub OS1 so as to return to the PLL circuit 11, and do not reach the filter circuit 12.

摘要翻译： 本发明的目的是提供一种用于半导体器件的半导体器件和调整方法，其中可以减少作为无线电波辐射的电源噪声和噪声，并且可以切割半导体器件内部的电源噪声。 开放短截线OS1形成在半导体器件1的上部布线层中。 短截线长度L 1被设定为包含噪声的峰值成分的已知频率的波长的1/4的长度。 噪声接收部分AT 1设置成与开放存根OS1相邻。 开路短路OS1通过层间配线6与电源配线4连接。 噪声接收部分AT 1被偏压到接地电位。 由PLL电路11产生并传播（图2中的箭头Y 1）的基本波分量和奇数谐波在电源布线4中被反射（图2中的箭头Y 2）（图2中的箭头Y 2） 打开存根OS1，以返回到PLL电路11，并且不到达滤波电路12。