公开(公告)号：US07576585B2

公开(公告)日：2009-08-18

申请号：US12047162

申请日：2008-03-12

申请人： Shigetaka Asano ,  Kazuyoshi Kikuta

发明人： Shigetaka Asano ,  Kazuyoshi Kikuta

IPC分类号： H03H11/26

CPC分类号： H03K5/133 ,  H03K2005/00026 ,  H03K2005/00058

摘要： A delay circuit, including: a plurality of first delay units coupled in series and each configured to generate a delay time that is approximately double a unit delay time; a second delay unit configured to generate the unit delay time and coupled to a last stage of the plurality of first delay units; and a selector configured to select either an output signal of the last stage of the plurality of first delay units or an output signal of the second delay unit, wherein an external input signal is input to the first delay unit and to each second delay unit, and the first delay unit and the second delay unit each include a switch circuit configured to output with a delay either an output signal of a previous stage delay unit or the external input signal.

摘要翻译： 一种延迟电路，包括：串联耦合的多个第一延迟单元，每个被配置为产生大约是单位延迟时间的两倍的延迟时间; 第二延迟单元，被配置为产生所述单位延迟时间并耦合到所述多个第一延迟单元的最后一级; 以及选择器，其被配置为选择所述多个第一延迟单元的最后级的输出信号或所述第二延迟单元的输出信号，其中外部输入信号被输入到所述第一延迟单元和每个第二延迟单元， 并且第一延迟单元和第二延迟单元各自包括被配置为延迟输出前级延迟单元的输出信号或外部输入信号的开关电路。

公开(公告)号：US20080224751A1

公开(公告)日：2008-09-18

申请号：US12047162

申请日：2008-03-12

申请人： Shigetaka ASANO ,  Kazuyoshi Kikuta

发明人： Shigetaka ASANO ,  Kazuyoshi Kikuta

IPC分类号： H03H11/26

CPC分类号： H03K5/133 ,  H03K2005/00026 ,  H03K2005/00058

摘要： A delay circuit, including: a plurality of first delay units coupled in series and each configured to generate a delay time that is approximately double a unit delay time; a second delay unit configured to generate the unit delay time and coupled to a last stage of the plurality of first delay units; and a selector configured to select either an output signal of the last stage of the plurality of first delay units or an output signal of the second delay unit, wherein an external input signal is input to the first delay unit and to each second delay unit, and the first delay unit and the second delay unit each include a switch circuit configured to output with a delay either an output signal of a previous stage delay unit or the external input signal.

摘要翻译： 一种延迟电路，包括：串联耦合的多个第一延迟单元，每个被配置为产生大约是单位延迟时间的两倍的延迟时间; 第二延迟单元，被配置为产生所述单位延迟时间并耦合到所述多个第一延迟单元的最后一级; 以及选择器，其被配置为选择所述多个第一延迟单元的最后级的输出信号或所述第二延迟单元的输出信号，其中外部输入信号被输入到所述第一延迟单元和每个第二延迟单元， 并且第一延迟单元和第二延迟单元各自包括被配置为延迟输出前级延迟单元的输出信号或外部输入信号的开关电路。

公开(公告)号：US4975593A

公开(公告)日：1990-12-04

申请号：US255255

申请日：1988-10-11

申请人： Keiichi Kurakazu ,  Haruo Keida ,  Kazuyoshi Kikuta

发明人： Keiichi Kurakazu ,  Haruo Keida ,  Kazuyoshi Kikuta

IPC分类号： G06F13/38 ,  G06F1/04 ,  G06F1/12 ,  G06F13/42 ,  G06F15/78

CPC分类号： G06F1/04 ,  G06F13/423

摘要： A single-chip microcomputer has external terminals outputting a system clock signal, an address signal, and a data signals. External equipment such as an external memory is operated by address and signal which are output when the system clock signal changes. In the single-chip microcomputer of this invention, the operation of an address signal output circuit and that of a data signal output circuit are controlled by a signal output from a digital delay circuit which receives the system clock signal. According to this circuit construction, the hold time between the change in the system clock and the change in the address and data signals is determined by the delay circuit which exhibits a digital operation, so that the hold time can be set accurately without being affected adversely by any variation in the circuit elements due to the manufacturing process, or by temperature changes.

摘要翻译： 单片机具有输出系统时钟信号，地址信号和数据信号的外部端子。 外部设备（如外部存储器）由系统时钟信号变化时输出的地址和信号进行操作。 在本发明的单片机中，地址信号输出电路和数据信号输出电路的动作由接收系统时钟信号的数字延迟电路输出的信号进行控制。 根据该电路结构，系统时钟的变化与地址和数据信号的变化之间的保持时间由展现数字操作的延迟电路确定，使得可以准确地设定保持时间而不受不利影响 由于制造过程中的电路元件的任何变化，或通过温度变化。

公开(公告)号：US06671112B2

公开(公告)日：2003-12-30

申请号：US10023769

申请日：2001-12-21

申请人： Hiroko Murakami ,  Masaru Sawada ,  Manabu Nakano ,  Kazuyoshi Kikuta

发明人： Hiroko Murakami ,  Masaru Sawada ,  Manabu Nakano ,  Kazuyoshi Kikuta

IPC分类号： G11B509

CPC分类号： H03L7/0993 ,  G11B5/012 ,  G11B5/553 ,  G11B5/59622 ,  H03L7/091

摘要： A digital arithmetic operation circuit includes a plurality of arithmetic operation blocks, a control signal generator and a selector. The plurality of arithmetic operation blocks receive a plurality of digital input signals and perform different arithmetic operations on the received digital input signals, in parallel, to output operation result signals. The a control signal generator receives a plurality of digital input signals and generates a control signal based on the digital input signals. The selector selects one of the operation result signals, in response to the control signal, to output the selected operation result signal. After the control signal generator supplies the control signal to the selector, the selector outputs the selected operation result signal as soon as the selected operation result signal is supplied to the selector.

摘要翻译： 数字运算电路包括多个算术运算块，控制信号发生器和选择器。 多个算术运算块并行地接收多个数字输入信号，并对接收的数字输入信号进行不同的算术运算，以输出运算结果信号。 控制信号发生器接收多个数字输入信号，并根据数字输入信号产生控制信号。 选择器响应于控制信号选择一个操作结果信号，以输出所选择的运算结果信号。 在控制信号发生器将控制信号提供给选择器之后，一旦选择的操作结果信号被提供给选择器，选择器输出所选择的运算结果信号。

公开(公告)号：US06377416B1

公开(公告)日：2002-04-23

申请号：US09192497

申请日：1998-11-17

申请人： Kazuyoshi Kikuta

发明人： Kazuyoshi Kikuta

IPC分类号： G11B5596

CPC分类号： H03L7/0993 ,  G11B5/012 ,  G11B5/553 ,  G11B5/59622 ,  H03L7/091

摘要： A digital arithmetic operation circuit includes a plurality of arithmetic operation blocks, a control signal generator and a selector. The plurality of arithmetic operation blocks receive a plurality of digital input signals and perform different arithmetic operations on the received digital input signals, in parallel, to output operation result signals. The a control signal generator receives a plurality of digital input signals and generates a control signal based on the digital input signals. The selector selects one of the operation result signals, in response to the control signal, to output the selected operation result signal. After the control signal generator supplies the control signal to the selector, the selector outputs the selected operation result signal as soon as the selected operation result signal is supplied to the selector.

摘要翻译： 数字运算电路包括多个算术运算块，控制信号发生器和选择器。 多个算术运算块并行地接收多个数字输入信号，并对接收的数字输入信号进行不同的算术运算，以输出运算结果信号。 控制信号发生器接收多个数字输入信号，并根据数字输入信号产生控制信号。 选择器响应于控制信号选择一个操作结果信号，以输出所选择的运算结果信号。 在控制信号发生器将控制信号提供给选择器之后，一旦选择的操作结果信号被提供给选择器，选择器输出所选择的运算结果信号。

公开(公告)号：US5604723A

公开(公告)日：1997-02-18

申请号：US642575

申请日：1991-01-17

申请人： Kazuyoshi Kikuta

发明人： Kazuyoshi Kikuta

IPC分类号： G06K7/00 ,  G11B7/013 ,  G11B20/12 ,  G11B20/14 ,  G11B27/30 ,  G11B7/00

CPC分类号： G11B20/12 ,  G11B20/1403 ,  G11B27/3027 ,  G11B7/013 ,  G11B2020/1476 ,  G11B2220/218

摘要： This invention relates to a method and apparatus for reading out a synchronizing signal recorded in a data portion of each of a number of sectors stored in a recording medium such as an optical disc, a write-in-once type magneto-optical disc and so on. Even when detection of a synchronizing a signal has failed, the succeeding re-synchronizing signal can be detected reliably so that, although a first one divided unit portion of data is dropped out, data following the re-synchronizing signal can be read out positively, thus reducing data read error rate.

摘要翻译： 本发明涉及一种用于读出记录在存储在诸如光盘，一次写入型光磁盘等的记录介质中的多个扇区的每个扇区的数据部分中的同步信号的方法和装置 上。 即使当同步信号的检测失败时，可以可靠地检测到后续的再同步信号，使得尽管数据的第一个分割单位部分被丢弃，但可以肯定地读出重新同步信号之后的数据， 从而降低数据读取错误率。