公开(公告)号：US07932507B2

公开(公告)日：2011-04-26

申请号：US12727672

申请日：2010-03-19

申请人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

发明人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

IPC分类号： H01L29/02

CPC分类号： B82Y10/00 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

摘要： A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

摘要翻译： 使用具有大约10nm的尺寸的纳米颗粒层形成电流收缩层或作为用于从下面的绝​​缘体层形成电流收缩层的硬掩模。 纳米颗粒优选在下面的表面上自对准和/或自平坦化。 电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电 材料。 电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。 由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

公开(公告)号：US08138028B2

公开(公告)日：2012-03-20

申请号：US11764678

申请日：2007-06-18

申请人： Hsiang Lan Lung ,  Chieh Fang Chen ,  Yi Chou Chen ,  Shih Hung Chen ,  Chung Hon Lam ,  Eric Andrew Joseph ,  Alejandro Gabriel Schrott ,  Matthew J. Breitwisch ,  Geoffrey William Burr ,  Thomas D. Happ ,  Jan Boris Philipp

发明人： Hsiang Lan Lung ,  Chieh Fang Chen ,  Yi Chou Chen ,  Shih Hung Chen ,  Chung Hon Lam ,  Eric Andrew Joseph ,  Alejandro Gabriel Schrott ,  Matthew J. Breitwisch ,  Geoffrey William Burr ,  Thomas D. Happ ,  Jan Boris Philipp

IPC分类号： H01L45/00

CPC分类号： H01L45/144 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/14 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

摘要： A method for manufacturing a mushroom-cell type phase change memory is based upon manufacturing a pillar of bottom electrode material upon a substrate including an array of conductive contacts in electrical communication with access circuitry. A layer of electrode material is deposited making reliable electrical contact with the array of conductive contacts. Electrode material is etched to form a pattern of electrode pillars on corresponding conductive contacts. Next, a dielectric material is deposited over the pattern and planarized to provide an electrode surface exposing top surfaces of the electrode pillars. Next, a layer of programmable resistive material, such as a chalcogenide or other phase change material, is deposited, followed by deposition of a layer of a top electrode material. A device including bottom electrode pillars with larger bottom surfaces than top surfaces is described.

摘要翻译： 用于制造蘑菇细胞型相变存储器的方法是基于在包括与接入电路电连通的导电触点阵列的基板上制造底部电极材料的柱。 沉积一层电极材料，使其与导电触点阵列可靠地电接触。 蚀刻电极材料以在对应的导电触点上形成电极柱的图案。 接下来，将介电材料沉积在图案上并且被平坦化以提供暴露电极柱顶表面的电极表面。 接下来，沉积诸如硫族化物或其它相变材料的可编程电阻材料层，随后沉积顶层电极材料层。 描述了包括具有比顶表面更大的底表面的底部电极柱的装置。

公开(公告)号：US20080137400A1

公开(公告)日：2008-06-12

申请号：US11567361

申请日：2006-12-06

申请人： Shih Hung Chen ,  Hsiang Lan Lung ,  Yi-Chou Chen

发明人： Shih Hung Chen ,  Hsiang Lan Lung ,  Yi-Chou Chen

IPC分类号： G11C11/00 ,  H01L21/02

CPC分类号： H01L45/06 ,  G11C8/10 ,  G11C13/0004 ,  G11C2213/79 ,  H01L21/76834 ,  H01L21/76877 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675 ,  H01L45/1691

摘要： A memory cell has thermal isolation material between a bottom electrode and a plug contact to confine heat in a memory element during programming and reset operations. In a particular embodiment, the memory element is a chalcogenide, such as GST. An electrically conductive barrier layer deposited over the contact and on sidewalls of a recess formed over the contact electrically couples the bottom electrode to the contact.

摘要翻译： 存储单元在底电极和插头触点之间具有热隔离材料，以在编程和复位操作期间将热量限制在存储元件中。 在特定实施例中，存储元件是硫属化物，例如GST。 沉积在接触件上方的形成在触点上的凹部的侧壁上的导电阻挡层将底部电极电耦合到触点。

公开(公告)号：US20100193763A1

公开(公告)日：2010-08-05

申请号：US12727672

申请日：2010-03-19

申请人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

发明人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

IPC分类号： H01L45/00

CPC分类号： B82Y10/00 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

摘要： A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

摘要翻译： 使用具有大约10nm的尺寸的纳米颗粒层形成电流收缩层或作为用于从下面的绝​​缘体层形成电流收缩层的硬掩模。 纳米颗粒优选在下面的表面上自对准和/或自平坦化。 电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电 材料。 电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。 由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

公开(公告)号：US07745807B2

公开(公告)日：2010-06-29

申请号：US11776301

申请日：2007-07-11

申请人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

发明人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

IPC分类号： H01L29/02

CPC分类号： B82Y10/00 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

摘要： A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

摘要翻译： 使用具有大约10nm的尺寸的纳米颗粒层形成电流收缩层或作为用于从下面的绝​​缘体层形成电流收缩层的硬掩模。 纳米颗粒优选在下面的表面上自对准和/或自平坦化。 电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电 材料。 电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。 由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

公开(公告)号：US20090014704A1

公开(公告)日：2009-01-15

申请号：US11776301

申请日：2007-07-11

申请人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

发明人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

IPC分类号： H01L29/04

CPC分类号： B82Y10/00 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

摘要： A layer of nanopaiticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

摘要翻译： 使用具有大约10nm的尺寸的纳米颗粒层来形成电流收缩层或用作从底层绝缘体层形成电流收缩层的硬掩模。 纳米颗粒优选在下面的表面上自对准和/或自平坦化。 电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电 材料。 电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。 由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

公开(公告)号：US08237140B2

公开(公告)日：2012-08-07

申请号：US11424749

申请日：2006-06-16

申请人： Hsiang Lan Lung ,  Shih Hung Chen

发明人： Hsiang Lan Lung ,  Shih Hung Chen

IPC分类号： H01L45/00

CPC分类号： H01L27/2436 ,  G11C13/0004 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1293 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683 ,  H01L45/1691

摘要： An integrated circuit with an embedded memory comprises a substrate and a plurality of conductor layers arranged for interconnecting components of the integrated circuit. An intermediate layer in the plurality of conductor layers includes a first electrode having a top surface, a second electrode having a top surface, an insulating member between the first electrode and the second electrode. A bridge overlies the intermediate layer between the first and second electrodes across the insulating member, wherein the bridge comprises a programmable resistive memory material, such as a phase change material. A conductor in at least one layer in the plurality of conductor layers over said intermediate layer is connected to said bridge.

摘要翻译： 具有嵌入式存储器的集成电路包括衬底和布置用于互连集成电路的部件的多个导体层。 多个导体层中的中间层包括具有顶表面的第一电极，具有顶表面的第二电极，在第一电极和第二电极之间的绝缘构件。 桥跨过绝缘构件覆盖在第一和第二电极之间的中间层，其中桥包括可编程电阻存储器材料，例如相变材料。 在所述中间层上的多个导体层中的至少一层中的导体连接到所述桥。

公开(公告)号：US07635855B2

公开(公告)日：2009-12-22

申请号：US11348848

申请日：2006-02-07

申请人： Shih Hung Chen ,  Hsiang Lan Lung

发明人： Shih Hung Chen ,  Hsiang Lan Lung

IPC分类号： H01L47/00

CPC分类号： H01L27/2436 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

摘要： A memory device includes two electrodes, vertically separated and having mutually opposed contact surfaces, between which lies a phase change cell. The phase change cell includes an upper phase change member, having a contact surface in electrical contact with the first electrode; a lower phase change member, having a contact surface in electrical contact with the second electrode; and a kernel member disposed between and in electrical contact with the upper and lower phase change members. The phase change cell is formed of material having at least two solid phases, and the lateral extent of the upper and lower phase change members is substantially greater than that of the kernel member. An intermediate insulating layer is disposed between the upper and lower phase change members adjacent to the kernel member.

摘要翻译： 存储器件包括垂直分离并具有相互相对的接触表面的两个电极，它们位于相变单元之间。 相变单元包括上相变构件，具有与第一电极电接触的接触表面; 下部相变构件，具有与第二电极电接触的接触表面; 以及设置在上部和下部相变构件之间并与之电连接的内部构件。 相变单元由具有至少两个固相的材料形成，并且上下相变构件的横向范围基本上大于内核构件的横向范围。 中间绝缘层设置在与内核构件相邻的上下相变构件之间。

公开(公告)号：US07514334B2

公开(公告)日：2009-04-07

申请号：US11754559

申请日：2007-05-29

申请人： Shih Hung Chen ,  Hsiang Lan Lung

发明人： Shih Hung Chen ,  Hsiang Lan Lung

IPC分类号： H01L21/20 ,  H01L21/8234 ,  H01L21/336

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1691

摘要： A memory device comprising a access circuits, an electrode layer over the access circuits, an array of phase change memory bridges over the electrode layer, and a plurality of bit lines over the array of phase change memory bridges. The electrode layer includes electrode pairs. Electrode pairs include a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. A bridge of memory material crosses the insulating member, and defines an inter-electrode path between the first and second electrodes across the insulating member.

摘要翻译： 一种存储器件，包括存取电路，存取电路上的电极层，电极层上的相变存储器阵列，以及相变存储器桥阵列上的多个位线。 电极层包括电极对。 电极对包括具有顶侧的第一电极，具有顶侧的第二电极和在第一电极和第二电极之间的绝缘构件。 记忆材料桥跨越绝缘构件，并且在绝缘构件之间限定了第一和第二电极之间的电极间路径。

公开(公告)号：US07514367B2

公开(公告)日：2009-04-07

申请号：US11382739

申请日：2006-05-11

申请人： Hsiang Lan Lung ,  Chiahua Ho ,  Shih Hung Chen ,  Chieh Fang Chen

发明人： Hsiang Lan Lung ,  Chiahua Ho ,  Shih Hung Chen ,  Chieh Fang Chen

IPC分类号： H01L21/302

CPC分类号： H01L45/1226 ,  G11C13/0004 ,  H01L45/04 ,  H01L45/06 ,  H01L45/14 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1691 ,  Y10S438/947

摘要： A method of manufacturing for providing a narrow line, such as a phase change bridge, on a substrate having a top surface, includes first forming a layer of first material on the substrate. Then, a layer of a pattern material is applied on the layer of first material, and a pattern is defined. The pattern includes a ledge having a sidewall extending substantially to the layer of first material. A sidewall etch mask is formed on the ledge, and used to define a line of the first material on the substrate having a width substantially determined by the width of the sidewall etch mask.

摘要翻译： 一种用于在具有顶表面的基底上提供诸如相变桥的窄线的制造方法包括首先在基底上形成第一材料层。 然后，将图案材料层施加在第一材料层上，并且限定图案。 该图案包括具有基本上延伸到第一材料层的侧壁的凸缘。 侧壁蚀刻掩模形成在凸缘上，并且用于限定基板上的第一材料的线，其宽度基本上由侧壁蚀刻掩模的宽度决定。