公开(公告)号：US07706148B2

公开(公告)日：2010-04-27

申请号：US11588914

申请日：2006-10-27

申请人： Shih Ping Hsu ,  Chung Cheng Lien ,  Chia Wei Chang

发明人： Shih Ping Hsu ,  Chung Cheng Lien ,  Chia Wei Chang

IPC分类号： H01R12/16

CPC分类号： H05K1/185 ,  H01L23/5385 ,  H01L23/5389 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/462 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2203/061 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/32145 ,  H01L2924/00015

摘要： A stack structure of circuit boards embedded with semiconductor chips is proposed. At least two circuit boards are provided. Each of the circuit boards includes circuit layers formed on surfaces thereof and at least one opening embedded with a semiconductor chip, wherein, the circuit layers have a plurality of conductive structures and electrically conductive pads, and the semiconductor chip has a plurality of electrode pads, and the conductive structures of the circuit layers are electrically conductive to the electrode pads of the semiconductor chip. At least one adhesive layer is formed between the two circuit boards and disposed with a conductive material corresponding in position to the electrically conductive pads of the circuit boards. Thus, a conductive path can be formed by the conductive material between the electrically conductive pads of the circuit boards, thereby establishing electrical connection between the two circuit boards.

摘要翻译： 提出了嵌入半导体芯片的电路板的堆栈结构。 提供至少两个电路板。 每个电路板包括形成在其表面上的电路层和嵌入半导体芯片的至少一个开口，其中电路层具有多个导电结构和导电焊盘，并且半导体芯片具有多个电极焊盘， 并且电路层的导电结构与半导体芯片的电极焊盘导电。 在两个电路板之间形成至少一个粘合剂层，并且设置有与电路板的导电焊盘相对应的导电材料。 因此，可以通过导电材料在电路板的导电焊盘之间形成导电路径，由此建立两个电路板之间的电连接。

公开(公告)号：US20090091903A1

公开(公告)日：2009-04-09

申请号：US11588914

申请日：2006-10-27

申请人： Shih Ping Hsu ,  Chung Cheng Lien ,  Chia Wei Chang

发明人： Shih Ping Hsu ,  Chung Cheng Lien ,  Chia Wei Chang

IPC分类号： H05K1/18

CPC分类号： H05K1/185 ,  H01L23/5385 ,  H01L23/5389 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/462 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2203/061 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/32145 ,  H01L2924/00015

摘要： A stack structure of circuit boards embedded with semiconductor chips is proposed. At least two circuit boards are provided. Each of the circuit boards includes circuit layers formed on surfaces thereof and at least one opening embedded with a semiconductor chip, wherein, the circuit layers have a plurality of conductive structures and electrically conductive pads, and the semiconductor chip has a plurality of electrode pads, and the conductive structures of the circuit layers are electrically conductive to the electrode pads of the semiconductor chip. At least one adhesive layer is formed between the two circuit boards and disposed with a conductive material corresponding in position to the electrically conductive pads of the circuit boards. Thus, a conductive path can be formed by the conductive material between the electrically conductive pads of the circuit boards, thereby establishing electrical connection between the two circuit boards.

摘要翻译： 提出了嵌入半导体芯片的电路板的堆栈结构。 提供至少两个电路板。 每个电路板包括形成在其表面上的电路层和嵌入半导体芯片的至少一个开口，其中电路层具有多个导电结构和导电焊盘，并且半导体芯片具有多个电极焊盘， 并且电路层的导电结构与半导体芯片的电极焊盘导电。 在两个电路板之间形成至少一个粘合剂层，并且设置有与电路板的导电焊盘相对应的导电材料。 因此，可以通过导电材料在电路板的导电焊盘之间形成导电路径，由此建立两个电路板之间的电连接。

公开(公告)号：US07863729B2

公开(公告)日：2011-01-04

申请号：US12427668

申请日：2009-04-21

申请人： Shih Ping Hsu ,  Chung Cheng Lien ,  Shang Wei Chen

发明人： Shih Ping Hsu ,  Chung Cheng Lien ,  Shang Wei Chen

IPC分类号： H01L23/12 ,  H01L23/053

CPC分类号： H01L23/5389 ,  H01L23/13 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/18162 ,  H01L2924/351 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09809 ,  H05K2201/10674 ,  H01L2924/00

摘要： A circuit board structure embedded with semiconductor chips is proposed. A semiconductor chip is received in a cavity of a supporting board. A dielectric layer and a circuit layer are formed on the supporting board and the semiconductor chip. A plurality of hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the semiconductor chip. By providing the hollow conductive vias of present invention, the separating results of different coefficients of expansion and thermal stress are prevented, and thus electrical function of products is ensured.

摘要翻译： 提出了一种嵌入半导体芯片的电路板结构。 半导体芯片被容纳在支撑板的空腔中。 在支撑板和半导体芯片上形成电介质层和电路层。 在电介质层中形成多个中空导电通孔，用于将电路层与半导体芯片电连接。 通过提供本发明的中空导电通孔，可以防止不同膨胀系数和热应力的分离结果，从而确保产品的电功能。

公开(公告)号：US20070181995A1

公开(公告)日：2007-08-09

申请号：US11544199

申请日：2006-10-05

申请人： Shih Ping Hsu ,  Chung Cheng Lien ,  Shang Wei Chen

发明人： Shih Ping Hsu ,  Chung Cheng Lien ,  Shang Wei Chen

IPC分类号： H01L23/12

CPC分类号： H01L23/5389 ,  H01L23/13 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/18162 ,  H01L2924/351 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09809 ,  H05K2201/10674 ,  H01L2924/00

摘要： A circuit board structure embedded with semiconductor chips is proposed. A semiconductor chip is received in a cavity of a supporting board. A dielectric layer and a circuit layer are formed on the supporting board and the semiconductor chip. A plurality of hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the semiconductor chip. By providing the hollow conductive vias of present invention, the separating results of different coefficients of expansion and thermal stress are prevented, and thus electrical function of products is ensured.

摘要翻译： 提出了一种嵌入半导体芯片的电路板结构。 半导体芯片被容纳在支撑板的空腔中。 在支撑板和半导体芯片上形成电介质层和电路层。 在电介质层中形成多个中空导电通孔，用于将电路层与半导体芯片电连接。 通过提供本发明的中空导电通孔，可以防止不同膨胀系数和热应力的分离结果，从而确保产品的电功能。

公开(公告)号：US08058721B2

公开(公告)日：2011-11-15

申请号：US12535849

申请日：2009-08-05

申请人： Shih Ping Hsu

发明人： Shih Ping Hsu

IPC分类号： H01L23/538

CPC分类号： H05K1/185 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/221 ,  H01L2224/2518 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H05K3/4608

摘要： Disclosed is a package structure including a semiconductor chip disposed in a core board having a first surface and an opposite second surface. The package structure further includes a plurality of first and second electrode pads disposed on an active surface and an opposite inactive surface of the semiconductor chip respectively, the semiconductor chip having a plurality of through-silicon vias for electrically connecting the first and second electrode pads. As a result, the semiconductor chip is electrically connected to the two sides of the package structure via the through-silicon vias instead of conductive through holes, so as to enhance electrical quality and prevent the inactive surface of the semiconductor chip from occupying wiring layout space of the second surface of the core board to thereby increase wiring layout density and enhance electrical performance.

摘要翻译： 公开了包括设置在具有第一表面和相对的第二表面的芯板中的半导体芯片的封装结构。 封装结构还包括分别设置在半导体芯片的有源表面和相反的无效表面上的多个第一和第二电极焊盘，该半导体芯片具有用于电连接第一和第二电极焊盘的多个穿硅通孔。 结果，半导体芯片通过穿硅通孔而不是导电通孔电连接到封装结构的两侧，从而提高电气质量并防止半导体芯片的非激活表面占据布线布局空间 的芯板的第二表面，从而增加布线布局密度并增强电性能。

公开(公告)号：US20100032827A1

公开(公告)日：2010-02-11

申请号：US12535849

申请日：2009-08-05

申请人： Shih Ping Hsu

发明人： Shih Ping Hsu

IPC分类号： H01L23/538

CPC分类号： H05K1/185 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/221 ,  H01L2224/2518 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H05K3/4608

摘要： Disclosed is a package structure including a semiconductor chip disposed in a core board having a first surface and an opposite second surface. The package structure further includes a plurality of first and second electrode pads disposed on an active surface and an opposite inactive surface of the semiconductor chip respectively, the semiconductor chip having a plurality of through-silicon vias for electrically connecting the first and second electrode pads. As a result, the semiconductor chip is electrically connected to the two sides of the package structure via the through-silicon vias instead of conductive through holes, so as to enhance electrical quality and prevent the inactive surface of the semiconductor chip from occupying wiring layout space of the second surface of the core board to thereby increase wiring layout density and enhance electrical performance.

摘要翻译： 公开了包括设置在具有第一表面和相对的第二表面的芯板中的半导体芯片的封装结构。 封装结构还包括分别设置在半导体芯片的有源表面和相反的无效表面上的多个第一和第二电极焊盘，该半导体芯片具有用于电连接第一和第二电极焊盘的多个穿硅通孔。 结果，半导体芯片通过穿硅通孔而不是导电通孔电连接到封装结构的两侧，从而提高电气质量并防止半导体芯片的非激活表面占据布线布局空间 的芯板的第二表面，从而增加布线布局密度并增强电性能。