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    VARIABLE RESISTANCE NON-VOLATILE MEMORY CELLS AND METHODS OF FABRICATING SAME
    1.
    发明申请
    VARIABLE RESISTANCE NON-VOLATILE MEMORY CELLS AND METHODS OF FABRICATING SAME 有权
    可变电阻非挥发性记忆细胞及其制备方法

    公开(公告)号：US20080315174A1

    公开(公告)日：2008-12-25

    申请号：US11775657

    申请日：2007-07-10

    申请人： Shin-Jae Kang ,  Gyuhwan Oh ,  Insun Park ,  Hyunseok Lim ,  Nak-Hyun Lim

    发明人： Shin-Jae Kang ,  Gyuhwan Oh ,  Insun Park ,  Hyunseok Lim ,  Nak-Hyun Lim

    IPC分类号： H01L21/336 ,  H01L47/00

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    摘要： Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming a cup-shaped electrode on sidewalls of an opening in an insulation layer and through the opening on an ohmic layer that is stacked on a conductive structure. An insulation filling member is formed that at least partially fills an interior of the electrode. The insulation filling member is formed within a range of temperatures that is sufficiently low to not substantially change resistance of the ohmic layer. A variable resistivity material is formed on the insulation filling member and is electrically connected to the electrode.

    摘要翻译： 公开了制造集成电路存储单元和集成电路存储单元的方法。 可以通过在绝缘层中的开口的侧壁上形成杯形电极，并通过层叠在导电结构上的欧姆层上的开口来制造集成电路存储单元。 形成绝缘填充构件，其至少部分地填充电极的内部。 绝缘填充构件形成在足够低的温度范围内，而不能实质上改变欧姆层的电阻。 在绝缘填充构件上形成可变电阻率材料并与电极电连接。

    Variable resistance non-volatile memory cells and methods of fabricating same
    2.
    发明授权
    Variable resistance non-volatile memory cells and methods of fabricating same 有权
    可变电阻非易失性存储单元及其制造方法

    公开(公告)号：US07863173B2

    公开(公告)日：2011-01-04

    申请号：US11775657

    申请日：2007-07-10

    申请人： Shin-Jae Kang ,  Gyuhwan Oh ,  Insun Park ,  Hyunseok Lim ,  Nak-Hyun Lim

    发明人： Shin-Jae Kang ,  Gyuhwan Oh ,  Insun Park ,  Hyunseok Lim ,  Nak-Hyun Lim

    IPC分类号： H01L21/20

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    摘要： Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming a cup-shaped electrode on sidewalls of an opening in an insulation layer and through the opening on an ohmic layer that is stacked on a conductive structure. An insulation filling member is formed that at least partially fills an interior of the electrode. The insulation filling member is formed within a range of temperatures that is sufficiently low to not substantially change resistance of the ohmic layer. A variable resistivity material is formed on the insulation filling member and is electrically connected to the electrode.

    摘要翻译： 公开了制造集成电路存储单元和集成电路存储单元的方法。 可以通过在绝缘层中的开口的侧壁上形成杯形电极，并通过层叠在导电结构上的欧姆层上的开口来制造集成电路存储单元。 形成绝缘填充构件，其至少部分地填充电极的内部。 绝缘填充构件形成在足够低的温度范围内，而不能实质上改变欧姆层的电阻。 在绝缘填充构件上形成可变电阻率材料并与电极电连接。

    Multilevel semiconductor devices and methods of manufacturing the same
    3.
    发明申请
    Multilevel semiconductor devices and methods of manufacturing the same 审中-公开
    多层半导体器件及其制造方法

    公开(公告)号：US20060278985A1

    公开(公告)日：2006-12-14

    申请号：US11312441

    申请日：2005-12-21

    申请人： Hyunseok Lim ,  Jisoon Park ,  Dongjo Kang ,  Jungwook Kim ,  Insun Park ,  Hyunsuk Lee

    发明人： Hyunseok Lim ,  Jisoon Park ,  Dongjo Kang ,  Jungwook Kim ,  Insun Park ,  Hyunsuk Lee

    IPC分类号： H01L23/48

    CPC分类号： H01L27/0688 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/8221 ,  H01L23/485

    摘要： A multilevel semiconductor device and method of making the same includes a first active semiconductor structure, a first insulating layer on the first active semiconductor structure, a second active semiconductor structure on the first insulating layer and over the first active semiconductor structure, a second insulating layer on the second active semiconductor structure, and a contact structure including a first ohmic contact having a vertical thickness on an upper surface of the first active semiconductor structure and a second ohmic contact of a lateral thickness on a sidewall of the second active semiconductor structure, the vertical thickness being greater than the lateral thickness.

    摘要翻译： 多级半导体器件及其制造方法包括第一有源半导体结构，第一有源半导体结构上的第一绝缘层，第一绝缘层上和第一有源半导体结构上的第二有源半导体结构，第二绝缘层 在第二有源半导体结构上，以及包括在第一有源半导体结构的上表面上具有垂直厚度的第一欧姆接触和第二有源半导体结构的侧壁上的横向厚度的第二欧姆接触的接触结构， 垂直厚度大于横向厚度。