-
公开(公告)号：US08361900B2
公开(公告)日：2013-01-29
申请号：US12761805
申请日：2010-04-16
申请人： Shing-Chyang Pan , Han-Hsin Kuo , Chung-Chi Ko , Ching-Hua Hsieh
发明人： Shing-Chyang Pan , Han-Hsin Kuo , Chung-Chi Ko , Ching-Hua Hsieh
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76831 , H01L21/76844 , H01L21/76861 , H01L21/76867 , H01L21/76873 , H01L2221/1089
摘要： A copper interconnect includes a copper layer formed in a dielectric layer. A liner is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the liner and the dielectric layer. The barrier layer is a metal oxide.
摘要翻译： 铜互连包括在电介质层中形成的铜层。 在铜层和电介质层之间形成衬垫。 在衬垫和电介质层之间的边界处形成阻挡层。 阻挡层是金属氧化物。
-
公开(公告)号：US20130256659A1
公开(公告)日：2013-10-03
申请号：US13436952
申请日：2012-04-01
申请人： Chi-Ming Tsai , Liang-Guang Chen , Han-Hsin Kuo , Fu-Ming Huang , Hao-Jen Liao , Ming-Chung Liang
发明人： Chi-Ming Tsai , Liang-Guang Chen , Han-Hsin Kuo , Fu-Ming Huang , Hao-Jen Liao , Ming-Chung Liang
CPC分类号： H01L22/12 , H01L21/7684 , H01L22/30 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a substrate and an interconnect structure disposed over the substrate. The interconnect structure includes a plurality of interconnect layers. One of the interconnect layers contains: a plurality of metal via slots and a bulk metal component disposed over the plurality of metal via slots. The present disclosure also provides a method. The method includes providing a wafer, and forming a first layer over the wafer. The method includes forming an interconnect structure over the first layer. The forming the interconnect structure includes forming a second interconnect layer over the first layer, and forming a third interconnect layer over the second interconnect layer. The second interconnect layer is formed to contain a plurality of metal via slots and a bulk metal component formed over the plurality of metal via slots. The third interconnect layer contains one or more metal trenches.
摘要翻译： 本发明提供一种半导体器件。 半导体器件包括衬底和布置在衬底上的互连结构。 互连结构包括多个互连层。 互连层中的一个包含：多个金属通孔插槽和设置在多个金属通孔上的体金属部件。 本公开还提供了一种方法。 该方法包括提供晶片，并在晶片上形成第一层。 该方法包括在第一层上形成互连结构。 形成互连结构包括在第一层上形成第二互连层，以及在第二互连层上形成第三互连层。 第二互连层形成为包含多个金属通孔槽和形成在多个金属通孔上的体金属部件。 第三互连层包含一个或多个金属沟槽。
-
公开(公告)号：US20050170980A1
公开(公告)日：2005-08-04
申请号：US10769245
申请日：2004-01-30
申请人： Hsin-Hsien Lu , Han-Hsin Kuo , Ying-Ho Chen , Syum-Ming Jang
发明人： Hsin-Hsien Lu , Han-Hsin Kuo , Ying-Ho Chen , Syum-Ming Jang
CPC分类号： C11D7/262 , C11D7/261 , C11D11/0047 , H01L21/02074
摘要： A method for the cleaning of wafers typically during a chemical mechanical polishing (CMP) process. The method includes polishing a material layer on a wafer in sequential polishing steps, rinsing the wafer using a novel surfactant composition solution after at least one of the polishing steps and rinsing of the wafer using deionized water, respectively. The surfactant composition solution imparts a generally hydrophilic character to a hydrophobic material layer such as a high-k dielectric layer on the wafer. Consequently, the layer is rendered amenable to cleaning by deionized water, thereby significantly enhancing the removal of particles from the layer and reducing the number of defects related to the CMP process.
摘要翻译： 通常在化学机械抛光（CMP）工艺期间清洗晶片的方法。 该方法包括在顺序抛光步骤中抛光晶片上的材料层，在至少一个抛光步骤和使用去离子水冲洗晶片之后，使用新型表面活性剂组合物溶液冲洗晶片。 表面活性剂组合物溶液对疏水性材料层（例如晶片上的高k电介质层）具有普遍的亲水性。 因此，该层适于用去离子水清洗，从而显着增强颗粒从层中的去除并减少与CMP工艺相关的缺陷数量。
-
公开(公告)号：US20060112971A1
公开(公告)日：2006-06-01
申请号：US10999277
申请日：2004-11-30
申请人： Han-Hsin Kuo , Hsin-Hsien Lu , Ying-Ho Chen , Syun-Ming Jang
发明人： Han-Hsin Kuo , Hsin-Hsien Lu , Ying-Ho Chen , Syun-Ming Jang
CPC分类号： H01L21/02074 , C23G1/00
摘要： A method for cleaning a semiconductor wafer surface comprises sweeping the semiconductor wafer surface and applying a first cleaning solution having a first pH, stop applying the first cleaning solution and applying a first rinsing solution to the semiconductor wafer surface, the first rinsing solution having a second pH that is significantly different from the first pH, sweeping the semiconductor wafer surface and applying a second cleaning solution having a third pH, and stop applying the second cleaning solution and applying a second rinsing solution to the semiconductor wafer surface, the second rinsing solution having a fourth pH that is significantly different from the third pH.
摘要翻译： 一种清洗半导体晶片表面的方法，包括扫描半导体晶片表面并施加具有第一pH值的第一清洗溶液，停止施加第一清洗溶液并向半导体晶片表面施加第一冲洗溶液，第一冲洗溶液具有第二 pH与第一pH显着不同，扫描半导体晶片表面并施加具有第三pH的第二清洗溶液，并停止施加第二清洗溶液并将第二冲洗溶液施加到半导体晶片表面，第二冲洗溶液具有 与第三pH显着不同的第四个pH。
-
公开(公告)号：US09252060B2
公开(公告)日：2016-02-02
申请号：US13436952
申请日：2012-04-01
申请人： Chi-Ming Tsai , Liang-Guang Chen , Han-Hsin Kuo , Fu-Ming Huang , Hao-Jen Liao , Ming-Chung Liang
发明人： Chi-Ming Tsai , Liang-Guang Chen , Han-Hsin Kuo , Fu-Ming Huang , Hao-Jen Liao , Ming-Chung Liang
IPC分类号： H01L23/58 , H01L21/66 , H01L23/522 , H01L21/768
CPC分类号： H01L22/12 , H01L21/7684 , H01L22/30 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a substrate and an interconnect structure disposed over the substrate. The interconnect structure includes a plurality of interconnect layers. One of the interconnect layers contains: a plurality of metal via slots and a bulk metal component disposed over the plurality of metal via slots. The present disclosure also provides a method. The method includes providing a wafer, and forming a first layer over the wafer. The method includes forming an interconnect structure over the first layer. The forming the interconnect structure includes forming a second interconnect layer over the first layer, and forming a third interconnect layer over the second interconnect layer. The second interconnect layer is formed to contain a plurality of metal via slots and a bulk metal component formed over the plurality of metal via slots. The third interconnect layer contains one or more metal trenches.
摘要翻译： 本发明提供一种半导体器件。 半导体器件包括衬底和布置在衬底上的互连结构。 互连结构包括多个互连层。 互连层中的一个包含：多个金属通孔插槽和设置在多个金属通孔上的体金属部件。 本公开还提供了一种方法。 该方法包括提供晶片，并在晶片上形成第一层。 该方法包括在第一层上形成互连结构。 形成互连结构包括在第一层上形成第二互连层，以及在第二互连层上形成第三互连层。 第二互连层形成为包含多个金属通孔槽和形成在多个金属通孔上的体金属部件。 第三互连层包含一个或多个金属沟槽。
-
公开(公告)号：US09119464B2
公开(公告)日：2015-09-01
申请号：US13362635
申请日：2012-01-31
申请人： Fu-Ming Huang , Liang-Guang Chen , Han-Hsin Kuo , Chi-Ming Tsai , He Hui Peng
发明人： Fu-Ming Huang , Liang-Guang Chen , Han-Hsin Kuo , Chi-Ming Tsai , He Hui Peng
CPC分类号： A46B17/06 , A46B15/0018 , B08B1/007 , B08B6/00
摘要： A brush cleaning system comprising: a plate comprising at least one of silicon nitride (SixNy) or silicon oxide (SiaOb), wherein the plate has a static charge on a surface thereof; and a machine configured to rotate a brush in contact with the static charged surface of the plate.
摘要翻译： 一种刷清洁系统，包括：包含氮化硅（SixNy）或氧化硅（SiaOb）中的至少一种的板，其中所述板在其表面上具有静电荷; 以及机器，被配置为旋转与所述板的静电带电表面接触的刷子。
-
公开(公告)号：US08673783B2
公开(公告)日：2014-03-18
申请号：US12829664
申请日：2010-07-02
IPC分类号： H01L21/302
CPC分类号： H01L23/5386 , H01L21/02074 , H01L21/28079 , H01L21/67011 , H01L21/7684 , H01L29/495 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment.
摘要翻译： 本公开提供了一种制造半导体器件的方法，通过这种方法制造的半导体器件和用于执行这种方法的化学机械抛光（CMP）工具。 在一个实施例中，制造半导体器件的方法包括在衬底上的电介质层的沟槽中提供包括金属导体的集成电路（IC）晶片，以及执行化学机械抛光（CMP）工艺以平坦化金属导体 和电介质层。 该方法还包括清洁平坦化的金属导体和电介质层以除去CMP工艺中的残留物，用醇漂洗清洁的金属导体和介电层，并在惰性气体环境中干燥漂洗的金属导体和电介质层。
-
公开(公告)号：US20120001262A1
公开(公告)日：2012-01-05
申请号：US12829664
申请日：2010-07-02
IPC分类号： H01L29/78 , B24B7/00 , H01L21/306
CPC分类号： H01L23/5386 , H01L21/02074 , H01L21/28079 , H01L21/67011 , H01L21/7684 , H01L29/495 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment.
摘要翻译： 本公开提供了一种制造半导体器件的方法，通过这种方法制造的半导体器件和用于执行这种方法的化学机械抛光（CMP）工具。 在一个实施例中，制造半导体器件的方法包括在衬底上的电介质层的沟槽中提供包括金属导体的集成电路（IC）晶片，以及执行化学机械抛光（CMP）工艺以平坦化金属导体 和电介质层。 该方法还包括清洁平坦化的金属导体和电介质层以除去CMP工艺中的残留物，用醇漂洗清洁的金属导体和介电层，并在惰性气体环境中干燥漂洗的金属导体和电介质层。
-
公开(公告)号：US07091126B2
公开(公告)日：2006-08-15
申请号：US10422443
申请日：2003-04-24
申请人： Han-Hsin Kuo , Hung-Wen Su , Wen-Chih Chiou , Tsu Shih , Hsien-Ming Lee
发明人： Han-Hsin Kuo , Hung-Wen Su , Wen-Chih Chiou , Tsu Shih , Hsien-Ming Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/76886 , H01L21/32115 , H01L21/3212 , H01L21/7684
摘要： An improvement in a copper damascene process is disclosed. The improvement comprises the step of projecting an electron beam on to a chemical mechanically polished material surface having copper filled etched trenches at a known angle of incidence with respect to the material surface for a known period of time, the electron beam having a beamwidth substantially covering the material surface and a known intensity.
摘要翻译： 披露了铜镶嵌工艺的改进。 该改进包括将电子束投射到具有铜填充的蚀刻沟槽的化学机械抛光的材料表面上的步骤，其具有相对于材料表面已知的入射角已知的时间段，电子束具有基本覆盖的波束宽度 材料表面和已知的强度。
-
-
-
-
-
-
-
-
搜索结果
9 条记录 (耗时 0.024 秒)
