公开(公告)号：US20130153900A1

公开(公告)日：2013-06-20

申请号：US13818993

申请日：2011-08-26

申请人： Shinichi Kinouchi ,  Hiroshi Nakatake ,  Yuji Ebiike ,  Akihiko Furukawa ,  Masayuki Imaizumi

发明人： Shinichi Kinouchi ,  Hiroshi Nakatake ,  Yuji Ebiike ,  Akihiko Furukawa ,  Masayuki Imaizumi

IPC分类号： H01L23/34

CPC分类号： H01L23/34 ,  G01K7/01 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7803 ,  H01L29/7815 ,  H01L29/7828 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device capable of rapidly and accurately sensing the information regarding the temperature of a semiconductor transistor contained therein. A MOSFET includes a plurality of cells, and includes a main cell group including a cell for supplying a current to a load among the plurality of cells, and a sense cell group including a cell for sensing temperature information regarding the temperature of the MOSFET thereamong. The main cell group and the sense cell group have different temperature characteristics showing changes in electrical characteristics to changes in temperature. A temperature sensing circuit senses the temperature of the MOSFET based on, for example, a value of a main current flowing through the main cell group and a value of a sense current flowing through the sense cell group.

摘要翻译： 一种半导体器件，其能够快速且准确地感测关于其中包含的半导体晶体管的温度的信息。 MOSFET包括多个单元，并且包括主单元组，其包括用于向多个单元之间的负载提供电流的单元，以及包括用于感测关于MOSFET的温度的温度信息的单元的感测单元组。 主电池组和感应电池组具有不同的温度特性，显示电特性随温度变化的变化。 温度检测电路基于例如流过主单元组的主电流的值和流过感测单元组的感测电流的值来感测MOSFET的温度。

公开(公告)号：US08785931B2

公开(公告)日：2014-07-22

申请号：US13818993

申请日：2011-08-26

申请人： Shinichi Kinouchi ,  Hiroshi Nakatake ,  Yuji Ebiike ,  Akihiko Furukawa ,  Masayuki Imaizumi

发明人： Shinichi Kinouchi ,  Hiroshi Nakatake ,  Yuji Ebiike ,  Akihiko Furukawa ,  Masayuki Imaizumi

IPC分类号： H01L23/58 ,  H01L29/78

CPC分类号： H01L23/34 ,  G01K7/01 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7803 ,  H01L29/7815 ,  H01L29/7828 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device capable of rapidly and accurately sensing the information regarding the temperature of a semiconductor transistor contained therein. A MOSFET includes a plurality of cells, and includes a main cell group including a cell for supplying a current to a load among the plurality of cells, and a sense cell group including a cell for sensing temperature information regarding the temperature of the MOSFET thereamong. The main cell group and the sense cell group have different temperature characteristics showing changes in electrical characteristics to changes in temperature. A temperature sensing circuit senses the temperature of the MOSFET based on, for example, a value of a main current flowing through the main cell group and a value of a sense current flowing through the sense cell group.

摘要翻译： 一种半导体器件，其能够快速且准确地感测关于其中包含的半导体晶体管的温度的信息。 MOSFET包括多个单元，并且包括主单元组，其包括用于向多个单元之间的负载提供电流的单元，以及包括用于感测关于MOSFET的温度的温度信息的单元的感测单元组。 主电池组和感应电池组具有不同的温度特性，显示电特性随温度变化的变化。 温度检测电路基于例如流过主单元组的主电流的值和流过感测单元组的感测电流的值来感测MOSFET的温度。

公开(公告)号：US20140077232A1

公开(公告)日：2014-03-20

申请号：US14116067

申请日：2012-03-07

申请人： Shiro Hino ,  Naruhisa Miura ,  Akihiko Furukawa ,  Yukiyasu Nakao ,  Tomokatsu Watanabe ,  Masayoshi Tarutani ,  Yuji Ebiike ,  Masayuki Imaizumi ,  Sunao Aya

发明人： Shiro Hino ,  Naruhisa Miura ,  Akihiko Furukawa ,  Yukiyasu Nakao ,  Tomokatsu Watanabe ,  Masayoshi Tarutani ,  Yuji Ebiike ,  Masayuki Imaizumi ,  Sunao Aya

IPC分类号： H01L29/16 ,  H01L29/78

CPC分类号： H01L29/1608 ,  H01L21/0485 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7816 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same. A semiconductor device according to the present invention comprises a drift layer formed on a semiconductor substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layer and each of the first well regions, a gate electrode selectively formed on the gate insulating film, a source contact hole penetrating through the gate insulating film and reaching the inside of each of the first well regions, and a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains.

摘要翻译： 能够抑制阈值电压的时间变化的半导体器件及其制造方法。 根据本发明的半导体器件包括形成在半导体衬底上的漂移层，形成在漂移层的表面层中的第一阱区彼此分开，形成在栅极绝缘膜上的栅极绝缘膜，在漂移层上延伸，每个 选择性地形成在栅极绝缘膜上的栅极电极，穿过栅极绝缘膜并到达每个第一阱区域的内部的源极接触孔以及至少形成在第一阱区上的残留压应力层， 源接触孔的侧表面，其中保持压缩应力。

公开(公告)号：US09093361B2

公开(公告)日：2015-07-28

申请号：US14116067

申请日：2012-03-07

申请人： Shiro Hino ,  Naruhisa Miura ,  Akihiko Furukawa ,  Yukiyasu Nakao ,  Tomokatsu Watanabe ,  Masayoshi Tarutani ,  Yuji Ebiike ,  Masayuki Imaizumi ,  Sunao Aya

发明人： Shiro Hino ,  Naruhisa Miura ,  Akihiko Furukawa ,  Yukiyasu Nakao ,  Tomokatsu Watanabe ,  Masayoshi Tarutani ,  Yuji Ebiike ,  Masayuki Imaizumi ,  Sunao Aya

IPC分类号： H01L29/76 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L21/04 ,  H01L29/417 ,  H01L29/06

CPC分类号： H01L29/1608 ,  H01L21/0485 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7816 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same. A semiconductor device according to the present invention comprises a drift layer formed on a semiconductor substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layer and each of the first well regions, a gate electrode selectively formed on the gate insulating film, a source contact hole penetrating through the gate insulating film and reaching the inside of each of the first well regions, and a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains.

摘要翻译： 能够抑制阈值电压的时间变化的半导体器件及其制造方法。 根据本发明的半导体器件包括形成在半导体衬底上的漂移层，形成在漂移层的表面层中的第一阱区彼此分开，形成在栅极绝缘膜上的栅极绝缘膜，在漂移层上延伸，每个 选择性地形成在栅极绝缘膜上的栅极电极，穿过栅极绝缘膜并到达每个第一阱区域的内部的源极接触孔以及至少形成在第一阱区上的残留压应力层， 源接触孔的侧表面，其中保持压缩应力。

公开(公告)号：US20140299891A1

公开(公告)日：2014-10-09

申请号：US14355737

申请日：2012-09-24

申请人： Shiro Hino ,  Naruhisa Miura ,  Akihiko Furukawa ,  Tomokatsu Watanabe ,  Kenichi Ohtsuka ,  Hiroshi Watanabe ,  Yuji Ebiike

发明人： Shiro Hino ,  Naruhisa Miura ,  Akihiko Furukawa ,  Tomokatsu Watanabe ,  Kenichi Ohtsuka ,  Hiroshi Watanabe ,  Yuji Ebiike

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/16

CPC分类号： H01L29/0619 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/808

摘要： A semiconductor device that can improve reliability while suppressing increase of a conduction loss or a switching loss. In the semiconductor device, when a two-dimensional shape on a main surface of the semiconductor substrate is an unit cell, the shape being a repeating unit of a plurality of well regions periodically disposed in a surface layer of a drift layer, one unit cell and another unit cell adjacent in an x-axis direction are disposed misaligned in a y-axis direction, and one unit cell and another unit cell adjacent in the y-axis direction are disposed misaligned in the x-axis direction.

摘要翻译： 一种半导体器件，其可以在抑制导通损耗的增加或开关损耗的同时提高可靠性。 在半导体装置中，当在半导体基板的主表面上的二维形状是单位电池时，形状是周期性地设置在漂移层的表面层中的多个阱区域的重复单元，一个单元电池 并且在x轴方向上相邻的另一个单元单元在y轴方向上不对准地设置，并且在y轴方向上相邻的一个单位单元和另一个单位单元在x轴方向上不对准地设置。

公开(公告)号：US09190468B2

公开(公告)日：2015-11-17

申请号：US14355737

申请日：2012-09-24

申请人： Shiro Hino ,  Naruhisa Miura ,  Akihiko Furukawa ,  Tomokatsu Watanabe ,  Kenichi Ohtsuka ,  Hiroshi Watanabe ,  Yuji Ebiike

发明人： Shiro Hino ,  Naruhisa Miura ,  Akihiko Furukawa ,  Tomokatsu Watanabe ,  Kenichi Ohtsuka ,  Hiroshi Watanabe ,  Yuji Ebiike

IPC分类号： H01L27/118 ,  H01L21/44 ,  H01L29/06 ,  H01L29/739 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/808

CPC分类号： H01L29/0619 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/808

摘要： A semiconductor device that can improve reliability while suppressing increase of a conduction loss or a switching loss. In the semiconductor device, when a two-dimensional shape on a main surface of the semiconductor substrate is an unit cell, the shape being a repeating unit of a plurality of well regions periodically disposed in a surface layer of a drift layer, one unit cell and another unit cell adjacent in an x-axis direction are disposed misaligned in a y-axis direction, and one unit cell and another unit cell adjacent in the y-axis direction are disposed misaligned in the x-axis direction.

摘要翻译： 一种半导体器件，其可以在抑制导通损耗的增加或开关损耗的同时提高可靠性。 在半导体装置中，当在半导体基板的主表面上的二维形状是单位电池时，形状是周期性地设置在漂移层的表面层中的多个阱区域的重复单元，一个单元电池 并且在x轴方向上相邻的另一个单元单元在y轴方向上不对准地设置，并且在y轴方向上相邻的一个单位单元和另一个单位单元在x轴方向上不对准地设置。

公开(公告)号：US20130288467A1

公开(公告)日：2013-10-31

申请号：US13979564

申请日：2011-06-09

申请人： Yuji Ebiike ,  Takahiro Nakatani ,  Hiroshi Watanabe ,  Yoshio Fujii ,  Sunao Aya ,  Yoshiyuki Nakaki ,  Tsuyoshi Kawakami ,  Shuhei Nakata

发明人： Yuji Ebiike ,  Takahiro Nakatani ,  Hiroshi Watanabe ,  Yoshio Fujii ,  Sunao Aya ,  Yoshiyuki Nakaki ,  Tsuyoshi Kawakami ,  Shuhei Nakata

IPC分类号： H01L21/266

CPC分类号： H01L21/266 ,  H01L21/0465 ,  H01L23/544 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/872 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (c) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer.

摘要翻译： 能够抑制高电场的产生和防止发生电介质击穿的半导体装置及其制造方法。 制造半导体器件的方法包括：（a）制备作为由第一导电类型的碳化硅半导体构成的接地的n +衬底，（b）通过使用抗蚀剂形成围绕n +衬底上的元件区域的凹陷结构 图案，以及（c）通过通过抗蚀剂图案的杂质注入，在凹陷结构的凹槽底表面和凹陷侧表面中形成作为第二导电类型的杂质层的保护环注入层，以及 凹陷结构被杂质层覆盖。

公开(公告)号：US09059086B2

公开(公告)日：2015-06-16

申请号：US13979564

申请日：2011-06-09

申请人： Yuji Ebiike ,  Takahiro Nakatani ,  Hiroshi Watanabe ,  Yoshio Fujii ,  Sunao Aya ,  Yoshiyuki Nakaki ,  Tsuyoshi Kawakami ,  Shuhei Nakata

发明人： Yuji Ebiike ,  Takahiro Nakatani ,  Hiroshi Watanabe ,  Yoshio Fujii ,  Sunao Aya ,  Yoshiyuki Nakaki ,  Tsuyoshi Kawakami ,  Shuhei Nakata

IPC分类号： H01L21/265 ,  H01L21/76 ,  H01L21/266 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L21/04 ,  H01L23/544

CPC分类号： H01L21/266 ,  H01L21/0465 ,  H01L23/544 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/872 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (d) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer.

摘要翻译： 能够抑制高电场的产生和防止发生电介质击穿的半导体装置及其制造方法。 制造半导体器件的方法包括：（a）制备作为由第一导电类型的碳化硅半导体构成的接地的n +衬底，（b）通过使用抗蚀剂形成围绕n +衬底上的元件区域的凹陷结构 图案，以及（d）通过通过抗蚀剂图案的杂质注入，在凹部结构的凹部底面和凹部侧面中形成作为第二导电类型的杂质层的保护环注入层，以及 凹陷结构被杂质层覆盖。