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    Semiconductor integrated circuit device and a method of manufacturing the same
    2.
    发明授权
    Semiconductor integrated circuit device and a method of manufacturing the same 有权
    半导体集成电路器件及其制造方法

    公开(公告)号：US08222712B2

    公开(公告)日：2012-07-17

    申请号：US12399957

    申请日：2009-03-08

    申请人： Kunihiko Kato ,  Shigeya Toyokawa ,  Kozo Watanabe ,  Masatoshi Taya

    发明人： Kunihiko Kato ,  Shigeya Toyokawa ,  Kozo Watanabe ,  Masatoshi Taya

    IPC分类号： H01L29/872

    CPC分类号： H01L29/872 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/417 ,  H01L2924/0002 ,  H01L2924/00

    摘要： To achieve a further reduction in the size of a finished product by reducing the number of externally embedded parts, the embedding of a Schottky barrier diode which is relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. In such a case, it is general practice to densely arrange a large number of contact electrodes in a matrix over a Schottky junction region. It has been widely performed to perform a sputter etching process with respect to the surface of a silicide layer at the bottom of each contact hole before a barrier metal layer is deposited. However, in a structure in which electrodes are thus arranged over a Schottky junction region, a reverse leakage current in a Schottky barrier diode is varied by variations in the amount of sputter etching. The present invention is a semiconductor integrated circuit device having a Schottky barrier diode in which contact electrodes are arranged over a guard ring in contact with a peripheral isolation region.

    摘要翻译： 为了通过减少外部嵌入部件的数量来进一步减小成品的尺寸，已经追求了在半导体集成电路器件中嵌入的电流量相对较大的肖特基势垒二极管。 在这种情况下，通常的做法是在肖特基结区域上将矩阵中的大量接触电极密集布置。 在阻挡金属层沉积之前，已经广泛地执行相对于每个接触孔底部的硅化物层的表面的溅射蚀刻工艺。 然而，在其中将电极布置在肖特基结区上方的结构中，肖特基势垒二极管中的反向泄漏电流由于溅射蚀刻量的变化而变化。 本发明是一种具有肖特基势垒二极管的半导体集成电路器件，其中接触电极布置在与周边隔离区接触的保护环上。

    SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME AND DESIGNING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME AND DESIGNING THE SAME 有权
    半导体器件及其制造方法及其设计方法

    公开(公告)号：US20120126360A1

    公开(公告)日：2012-05-24

    申请号：US13362385

    申请日：2012-01-31

    申请人： Kenichi KURODA ,  Kozo Watanabe ,  Hirohiko Yamamoto

    发明人： Kenichi KURODA ,  Kozo Watanabe ,  Hirohiko Yamamoto

    IPC分类号： H01L29/06

    CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

    摘要翻译： 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案， 在虚拟区域FA中。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

    SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME AND DESIGNING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME AND DESIGNING THE SAME 有权
    半导体器件及其制造方法及其设计方法

    公开(公告)号：US20110207288A1

    公开(公告)日：2011-08-25

    申请号：US13096246

    申请日：2011-04-28

    申请人： Kenichi KURODA ,  Kozo Watanabe ,  Hirohiko Yamamoto

    发明人： Kenichi KURODA ,  Kozo Watanabe ,  Hirohiko Yamamoto

    IPC分类号： H01L21/302

    CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

    摘要翻译： 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案， 在虚拟区域FA中。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

    SECONDARY BATTERY, BATTERY PACK INCLUDING SECONDARY BATTERY, AND METHOD FOR FABRICATING SECONDARY BATTERY
    5.
    发明申请
    SECONDARY BATTERY, BATTERY PACK INCLUDING SECONDARY BATTERY, AND METHOD FOR FABRICATING SECONDARY BATTERY 审中-公开
    二次电池，包括二次电池的电池组，以及制造二次电池的方法

    公开(公告)号：US20110135997A1

    公开(公告)日：2011-06-09

    申请号：US13058419

    申请日：2009-07-16

    申请人： Kozo Watanabe ,  Yoshiyuki Muraoka ,  Toshitada Sato ,  Mami Matsumoto

    发明人： Kozo Watanabe ,  Yoshiyuki Muraoka ,  Toshitada Sato ,  Mami Matsumoto

    IPC分类号： H01M2/02 ,  H01M10/04

    CPC分类号： H01M2/0212 ,  H01M2/0267 ,  H01M2/0275 ,  H01M2/1061 ,  Y10T29/49108 ,  Y10T29/4911 ,  Y10T29/49115

    摘要： The disclosed secondary battery is a flat secondary battery 10 including an electrode group 1 which is sealed in a laminate case 9 made of laminate films, and includes a positive electrode including a positive electrode current collector carrying thereon a positive electrode material mixture layer containing a positive electrode active material and a binder, a negative electrode, and a porous insulating layer. The laminate case 9 includes a container portion 9a for containing the electrode group 1, a weld portion 9b in which the laminate films are welded to each other, and a non-weld portion 9c which is provided between the container portion 9a and the weld portion 9b, and in which the laminate films are not welded to each other. The positive electrode has a tensile extension of 3.0% or higher.

    摘要翻译： 所公开的二次电池是平面二次电池10，其包括密封在由层压膜制成的层叠壳体9中的电极组1，并且包括正极，其包括正极集电体，该正极集电体承载包含正极的正极材料混合物层 电极活性物质和粘合剂，负极和多孔绝缘层。 层叠壳体9包括用于容纳电极组1的容器部分9a，层压膜彼此焊接的焊接部分9b和设置在容器部分9a和焊接部分之间的非焊接部分9c 9b，并且其中层压膜彼此不焊接。 正极的拉伸伸长率为3.0％以上。

    Method of manufacture of a semiconductor device
    6.
    发明授权
    Method of manufacture of a semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US07118972B2

    公开(公告)日：2006-10-10

    申请号：US10833118

    申请日：2004-04-28

    申请人： Masaaki Shinohara ,  Kozo Watanabe ,  Fukuo Owada ,  Takashi Aoyama

    发明人： Masaaki Shinohara ,  Kozo Watanabe ,  Fukuo Owada ,  Takashi Aoyama

    IPC分类号： H01L21/8234

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A method of manufacture of a semiconductor device uses simplified steps while improving the electrical properties of each element in the semiconductor device. Over a semiconductor substrate, having a memory gate electrode, control gate electrode and gate electrode formed thereover, a silicon oxide film, a silicon nitride film and a silicon oxide film are formed successively. The silicon oxide film formed over the gate electrode is then removed by wet etching. The silicon oxide film, silicon nitride film and silicon oxide film formed over the semiconductor substrate are removed successively by anisotropic dry etching, whereby respective sidewall spacers having a relatively large width and a relatively small width are formed.

    摘要翻译： 半导体器件的制造方法使用简化的步骤，同时改善半导体器件中每个元件的电性能。 在其上形成有存储栅电极，控制栅电极和栅电极的半导体衬底上，依次形成氧化硅膜，氮化硅膜和氧化硅膜。 然后通过湿蚀刻除去在栅电极上形成的氧化硅膜。 形成在半导体衬底上形成的氧化硅膜，氮化硅膜和氧化硅膜通过各向异性干蚀刻连续地去除，从而形成具有相对较大宽度和相对较小宽度的各个侧壁间隔物。

    Method of making a semiconductor memory circuit device
    8.
    发明授权
    Method of making a semiconductor memory circuit device 失效
    制造半导体存储器电路器件的方法

    公开(公告)号：US5389558A

    公开(公告)日：1995-02-14

    申请号：US104014

    申请日：1993-08-10

    申请人： Naokatsu Suwanai ,  Hiroyuki Miyazawa ,  Atushi Ogishima ,  Masaki Nagao ,  Kyoichiro Asayama ,  Hiroyuki Uchiyama ,  Yoshiyuki Kaneko ,  Takashi Yoneoka ,  Kozo Watanabe ,  Kazuya Endo ,  Hiroki Soeda

    发明人： Naokatsu Suwanai ,  Hiroyuki Miyazawa ,  Atushi Ogishima ,  Masaki Nagao ,  Kyoichiro Asayama ,  Hiroyuki Uchiyama ,  Yoshiyuki Kaneko ,  Takashi Yoneoka ,  Kozo Watanabe ,  Kazuya Endo ,  Hiroki Soeda

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10844 ,  H01L27/10805 ,  H01L27/10808

    摘要： In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.

    摘要翻译： 在其中每个存储单元由存储单元选择MISFET的串联电路和层叠结构的信息存储电容器构成的半导体存储器电路器件中，在第一区域中存在作为存储单元阵列区域的第一MISFET，其具有 栅极电极和源极和漏极区域; 第一和第二电容电极和延伸到栅电极上的第一绝缘膜上的电介质膜; 位于所述第二容量电极上的第二绝缘膜; 以及位于所述第二绝缘膜上的第一布线，而在作为外围电路区域的第二区域中存在具有栅极电极和源极和漏极区域的第二MISFET; 栅电极上的第一绝缘膜; 第一绝缘膜上的第三绝缘膜; 第三绝缘膜上的第二绝缘膜; 以及在第二绝缘膜上的第二布线。