公开(公告)号：US08437187B2

公开(公告)日：2013-05-07

申请号：US13232550

申请日：2011-09-14

申请人： Shinichi Yasuda ,  Masato Oda ,  Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

发明人： Shinichi Yasuda ,  Masato Oda ,  Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

IPC分类号： G11C16/04 ,  G11C7/10

CPC分类号： H03K19/17728 ,  G11C13/0002 ,  G11C16/0466 ,  H03K19/17768

摘要： In one embodiment, a semiconductor integrated circuit has memory cells. Each of the memory cells has non-volatile memories and switching elements. The non-volatile memories and switching elements are connected in series between a first power source and a second power source. Output wirings of at least two of the memory cells are connected to each other. Input wirings are connected with control gates of the switching elements included in each of the at least two memory cells. A plurality of the switching elements included in one of the at least two of the memory cells is turned off, when an input signal or an inverted signal is inputted. Further, another plurality of the switching elements included in another one of the at least two of memory cells other than the one of the memory cells is turned on, when the input signal or the inverted signal is inputted.

摘要翻译： 在一个实施例中，半导体集成电路具有存储单元。 每个存储单元具有非易失性存储器和开关元件。 非易失性存储器和开关元件串联连接在第一电源和第二电源之间。 至少两个存储单元的输出布线彼此连接。 输入布线与包括在至少两个存储单元中的每一个中的开关元件的控制栅极连接。 当输入信号或反相信号被输入时，包括在至少两个存储单元之一中的多个开关元件被断开。 此外，当输入信号或反相信号被输入时，包括在存储单元之外的至少两个存储单元中的另一个存储单元中的另外多个开关元件导通。

公开(公告)号：US20120230105A1

公开(公告)日：2012-09-13

申请号：US13232550

申请日：2011-09-14

申请人： Shinichi YASUDA ,  Masato Oda ,  Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

发明人： Shinichi YASUDA ,  Masato Oda ,  Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

IPC分类号： G11C16/04 ,  G11C5/06

CPC分类号： H03K19/17728 ,  G11C13/0002 ,  G11C16/0466 ,  H03K19/17768

摘要： In one embodiment, a semiconductor integrated circuit has memory cells. Each of the memory cells has non-volatile memories and switching elements. The non-volatile memories and switching elements are connected in series between a first power source and a second power source. Output wirings of at least two of the memory cells are connected to each other. Input wirings are connected with control gates of the switching elements included in each of the at least two memory cells. A plurality of the switching elements included in one of the at least two of the memory cells is turned off, when an input signal or an inverted signal is inputted. Further, another plurality of the switching elements included in another one of the at least two of memory cells other than the one of the memory cells is turned on, when the input signal or the inverted signal is inputted.

摘要翻译： 在一个实施例中，半导体集成电路具有存储单元。 每个存储单元具有非易失性存储器和开关元件。 非易失性存储器和开关元件串联连接在第一电源和第二电源之间。 至少两个存储单元的输出布线彼此连接。 输入布线与包括在至少两个存储单元中的每一个中的开关元件的控制栅极连接。 当输入信号或反相信号被输入时，包括在至少两个存储单元之一中的多个开关元件被断开。 此外，当输入信号或反相信号被输入时，包括在存储单元之外的至少两个存储单元中的另一个存储单元中的另外多个开关元件导通。

公开(公告)号：US08578318B2

公开(公告)日：2013-11-05

申请号：US13561483

申请日：2012-07-30

申请人： Kumiko Nomura ,  Shinichi Yasuda ,  Shinobu Fujita ,  Keiko Abe ,  Tetsufumi Tanamoto ,  Kazutaka Ikegami ,  Masato Oda

发明人： Kumiko Nomura ,  Shinichi Yasuda ,  Shinobu Fujita ,  Keiko Abe ,  Tetsufumi Tanamoto ,  Kazutaka Ikegami ,  Masato Oda

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5031 ,  G06F17/5054 ,  G06F17/5081

摘要： In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length.

摘要翻译： 在一个实施例中，一种用于实现集成电路的电路设计的方法包括：（a）获得第一布线以满足给定的工作频率; （b）基于给定的工作频率和第一布线的关键路径计算最大旁路布线长度; （c）通过在第一布线组中使用不同于第一布线的布线的旁路第一布线来获得第二布线，其中集成电路的布线被分类为多个布线组，并且第一布线包括在第一布线中 分类布线组的第一接线组; 以及（d）如果所述第二布线和所述第一布线之间的差不大于所述最大旁路布线长度，则用所述第二布线代替所述第一布线，并且如果所述差大于所述最大旁路布线，则不更换所述第一布线 长度。

公开(公告)号：US20130055189A1

公开(公告)日：2013-02-28

申请号：US13561483

申请日：2012-07-30

申请人： Kumiko Nomura ,  Shinichi Yasuda ,  Shinobu Fujita ,  Keiko Abe ,  Tetsufumi Tanamoto ,  Kazutaka Ikegami ,  Masato Oda

发明人： Kumiko Nomura ,  Shinichi Yasuda ,  Shinobu Fujita ,  Keiko Abe ,  Tetsufumi Tanamoto ,  Kazutaka Ikegami ,  Masato Oda

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5031 ,  G06F17/5054 ,  G06F17/5081

摘要： In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length.

摘要翻译： 在一个实施例中，一种用于实现集成电路的电路设计的方法包括：（a）获得第一布线以满足给定的工作频率; （b）基于给定的工作频率和第一布线的关键路径计算最大旁路布线长度; （c）通过在第一布线组中使用不同于第一布线的布线的旁路第一布线来获得第二布线，其中集成电路的布线被分类为多个布线组，并且第一布线包括在第一布线中 分类布线组的第一接线组; 以及（d）如果所述第二布线和所述第一布线之间的差不大于所述最大旁路布线长度，则用所述第二布线代替所述第一布线，并且如果所述差大于所述最大旁路布线，则不更换所述第一布线 长度。

公开(公告)号：US08680887B2

公开(公告)日：2014-03-25

申请号：US13419205

申请日：2012-03-13

申请人： Keiko Abe ,  Shinichi Yasuda ,  Kumiko Nomura ,  Shinobu Fujita

发明人： Keiko Abe ,  Shinichi Yasuda ,  Kumiko Nomura ,  Shinobu Fujita

IPC分类号： H03K19/177 ,  G11C11/34 ,  G11C16/04 ,  G11C11/00

CPC分类号： H03K19/1776 ,  G11C11/412 ,  G11C14/0063

摘要： According to one embodiment, a memory includes a first P-channel FET having a gate connected to a second output node, a source applied to a first potential, and a drain connected to the first output node, a second P-channel FET having a gate connected to a first output node, a source applied to the first potential, and a drain connected to the second output node, a first N-channel FET having a control gate connected to a first word line, a source applied to a second potential lower than the first potential, a drain connected to the first output node, and a threshold changed by data in a storage layer, and a second N-channel FET having a control gate connected to a second word line, a source applied to the second potential, a drain connected to the second output node, and a threshold changed by data in a storage layer.

摘要翻译： 根据一个实施例，存储器包括：第一P沟道FET，其具有连接到第二输出节点的栅极，施加到第一电位的源极和连接到第一输出节点的漏极;第二P沟道FET，其具有 连接到第一输出节点的源极，施加到第一电位的源极和连接到第二输出节点的漏极，具有连接到第一字线的控制栅极的第一N沟道FET，施加到第二电位的源极 低于第一电位的漏极，连接到第一输出节点的漏极和由存储层中的数据改变的阈值，以及具有连接到第二字线的控制栅极的第二N沟道FET，施加到第二电压的源极 电位，连接到第二输出节点的漏极以及由存储层中的数据改变的阈值。

公开(公告)号：US20120235705A1

公开(公告)日：2012-09-20

申请号：US13419205

申请日：2012-03-13

申请人： Keiko Abe ,  Shinichi Yasuda ,  Kumiko Nomura ,  Shinobu Fujita

发明人： Keiko Abe ,  Shinichi Yasuda ,  Kumiko Nomura ,  Shinobu Fujita

IPC分类号： H03K19/177 ,  G11C16/04

CPC分类号： H03K19/1776 ,  G11C11/412 ,  G11C14/0063

摘要： According to one embodiment, a memory includes a first P-channel FET having a gate connected to a second output node, a source applied to a first potential, and a drain connected to the first output node, a second P-channel FET having a gate connected to a first output node, a source applied to the first potential, and a drain connected to the second output node, a first N-channel FET having a control gate connected to a first word line, a source applied to a second potential lower than the first potential, a drain connected to the first output node, and a threshold changed by data in a storage layer, and a second N-channel FET having a control gate connected to a second word line, a source applied to the second potential, a drain connected to the second output node, and a threshold changed by data in a storage layer.

摘要翻译： 根据一个实施例，存储器包括：第一P沟道FET，其具有连接到第二输出节点的栅极，施加到第一电位的源极和连接到第一输出节点的漏极;第二P沟道FET，其具有 连接到第一输出节点的源极，施加到第一电位的源极和连接到第二输出节点的漏极，具有连接到第一字线的控制栅极的第一N沟道FET，施加到第二电位的源极 低于第一电位的漏极，连接到第一输出节点的漏极和由存储层中的数据改变的阈值，以及具有连接到第二字线的控制栅极的第二N沟道FET，施加到第二电压的源极 电位，连接到第二输出节点的漏极以及由存储层中的数据改变的阈值。

公开(公告)号：US08724403B2

公开(公告)日：2014-05-13

申请号：US13729382

申请日：2012-12-28

申请人： Kumiko Nomura ,  Shinobu Fujita ,  Keiko Abe ,  Kazutaka Ikegami ,  Hiroki Noguchi

发明人： Kumiko Nomura ,  Shinobu Fujita ,  Keiko Abe ,  Kazutaka Ikegami ,  Hiroki Noguchi

IPC分类号： G11C7/06

CPC分类号： G06F1/3206 ,  G06F1/3225 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

摘要： According to one embodiment, a cache system includes a tag memory includes a volatile memory device, the tag memory includes ways and storing a tag for each line, a data memory includes a nonvolatile memory device including sense amplifiers for reading data, the data memory includes ways and storing data for each line, a comparison circuit configured to compare a tag included in an address supplied from an external with a tag read from the tag memory, and a controller configured to turn off a power of a sense amplifier for a way which is not accessed based on a comparison result of the comparison circuit.

摘要翻译： 根据一个实施例，缓存系统包括标签存储器，其包括易失性存储器设备，标签存储器包括每条线路的方式和存储标签，数据存储器包括包括用于读取数据的读出放大器的非易失性存储器件，数据存储器包括 方式和存储每行的数据，比较电路，被配置为将从外部提供的地址中包含的标签与从标签存储器读取的标签进行比较，以及控制器，被配置为关闭读出放大器的功率， 基于比较电路的比较结果不被访问。

公开(公告)号：US20120233377A1

公开(公告)日：2012-09-13

申请号：US13234221

申请日：2011-09-16

申请人： Kumiko NOMURA ,  Keiko Abe ,  Shinobu Fujita

发明人： Kumiko NOMURA ,  Keiko Abe ,  Shinobu Fujita

IPC分类号： G06F12/08

CPC分类号： G06F12/0893 ,  Y02D10/13

摘要： According to an embodiment, a cache system includes a volatile cache memory, a nonvolatile cache memory, an address decoder, and an evacuation unit. The nonvolatile cache memory has a capacity equal to the volatile cache memory. The address decoder designates a same line to the volatile cache memory and the nonvolatile cache memory. The evacuation unit stores data which is inputted from the volatile cache memory and outputs the stored data to the volatile cache memory.

摘要翻译： 根据实施例，缓存系统包括易失性高速缓冲存储器，非易失性高速缓冲存储器，地址解码器和撤离单元。 非易失性高速缓冲存储器的容量等于易失性缓存存储器。 地址解码器指定与易失性高速缓冲存储器和非易失性高速缓冲存储器相同的行。 撤离单元存储从易失性高速缓冲存储器输入的数据，并将存储的数据输出到易失性高速缓冲存储器。

公开(公告)号：US09003128B2

公开(公告)日：2015-04-07

申请号：US13234837

申请日：2011-09-16

申请人： Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

发明人： Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0897 ,  G06F12/123 ,  G06F2212/225 ,  Y02D10/13

摘要： According to an embodiment, in a cache system, the sequence storage stores sequence data in association with each piece of data to be stored in the volatile cache memory in accordance with the number of pieces of data stored in the nonvolatile cache memory that have been unused for a longer period of time than the data stored in the volatile cache memory or the number of pieces of data stored in the nonvolatile cache memory that have been unused for a shorter period of time than the data stored in the volatile cache memory. The controller causes the first piece of data to be stored in the nonvolatile cache memory in a case where it can be determined that the first piece of data has been unused for a shorter period of time than any piece of the data stored in the nonvolatile cache memory.

摘要翻译： 根据实施例，在高速缓存系统中，序列存储器根据存储在非易失性高速缓冲存储器中的数据的数量与已经被使用的非易失性高速缓冲存储器中存储的数据数量相关联地存储与要存储在易失性高速缓存存储器中的每条数据相关联 比存储在易失性高速缓冲存储器中的数据或存储在非易失性高速缓冲存储器中的数据的时间长于存储在易失性高速缓冲存储器中的数据的时间长于较短时间段的更长时间段。 在可以确定第一条数据已被使用的时间短于存储在非易失性高速缓冲存储器中的任何数据的时间段的情况下，控制器使得第一条数据被存储在非易失性高速缓冲存储器中 记忆。

公开(公告)号：US08742810B2

公开(公告)日：2014-06-03

申请号：US13461101

申请日：2012-05-01

申请人： Hiroki Noguchi ,  Keiko Abe ,  Shinichi Yasuda ,  Shinobu Fujita

发明人： Hiroki Noguchi ,  Keiko Abe ,  Shinichi Yasuda ,  Shinobu Fujita

IPC分类号： H03L7/06

CPC分类号： H03L7/14 ,  H03L2207/18

摘要： One embodiment provides a phase-locked loop (PLL), in which a sequencer controls a loop filter such that, when a signal indicating turning-off of a power supply of the PLL is input thereto, or when a signal indicating turning-on of the power supply of the PLL is input thereto, a resistance value of a first resistance change device in the loop filter is a first resistance value, and that, after the PLL is stabilized, the resistance value of the first resistance change device is a second resistance value which is higher than the first resistance value.

摘要翻译： 一个实施例提供了一种锁相环（PLL），其中定序器控制环路滤波器，使得当指示关闭PLL的电源的信号被输入时，或者当指示接通 PLL的电源被输入到其中，环路滤波器中的第一电阻改变装置的电阻值是第一电阻值，并且在PLL稳定之后，第一电阻改变装置的电阻值是第二电阻值 电阻值高于第一电阻值。