Floating point data adder
    1.
    发明授权
    Floating point data adder 失效
    浮点数据加法器

    公开(公告)号:US4644490A

    公开(公告)日:1987-02-17

    申请号:US599167

    申请日:1984-04-11

    CPC分类号: G06F7/485 G06F2207/3884

    摘要: A pipelined adder for adding or subtracting two floating point input data each expressed by a sign data, an exponent data and a mantissa expressed in a sign-magnitude format, in accordance with an external operation mode designation signal to produce a floating point sum or difference data in a sign-magnitude format. In a first stage of the adder, the magnitudes of the exponent data of the input data are compared by a subtractor or a comparator and the magnitudes of the mantissa data of the input data are compared by a subtractor or a comparator. An actual operation mode for the mantissa data of the input data is determined, on the basis of the compare results of the exponent data and the mantissa data and the external operation mode designation signals, so that the operation result data is always expressed in a sign-magnitude format.

    摘要翻译: 一种流水线加法器,用于根据外部操作模式指定信号,加上或减去由符号数据,指数数据和符号幅度格式表示的尾数表示的两个浮点输入数据,以产生浮点和或差 数据格式的数据。 在加法器的第一级中,通过减法器或比较器比较输入数据的指数数据的大小,并通过减法器或比较器比较输入数据的尾数数据的大小。 基于指数数据和尾数数据和外部操作模式指定信号的比较结果确定输入数据的尾数数据的实际操作模式,使得操作结果数据总是以符号表示 -magnitude格式。

    Bus selection control in a data transmission apparatus for a
multiprocessor system
    4.
    发明授权
    Bus selection control in a data transmission apparatus for a multiprocessor system 失效
    用于多处理器系统的数据传输装置中的总线选择控制

    公开(公告)号:US4523272A

    公开(公告)日:1985-06-11

    申请号:US366785

    申请日:1982-04-08

    CPC分类号: G06F13/374

    摘要: In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferring bus request signals and bus control signals, and a bus controller for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is possible.

    摘要翻译: 在具有主存储器和通过公共地址总线连接的多个处理器,数据总线和用于数据传送的应答总线的多处理器系统中,为每个主存储器和处理器提供数据传输装置,并且包括总线请求控制线, 传送总线请求信号和总线控制信号;以及总线控制器,用于响应于总线请求控制线上的信号和请求信号单独控制地址总线,数据总线和应答总线的选择。 可以在一个周期内重叠处理,如数据写入和数据写入应答或数据读取和数据读取应答。

    Shared virtual address translation unit for a multiprocessor system
    5.
    发明授权
    Shared virtual address translation unit for a multiprocessor system 失效
    用于多处理器系统的共享虚拟地址转换单元

    公开(公告)号:US4481573A

    公开(公告)日:1984-11-06

    申请号:US320934

    申请日:1981-11-13

    IPC分类号: G06F12/08 G06F12/10 G06F13/00

    摘要: A virtual storage data processing system having an address translation unit shared by a plurality of processors, located in a memory control unit connected to a main memory is disclosed. One of the plurality of processors is a job processor which accesses the main memory with a virtual address to execute an instruction and includes a cache memory which is accessed with a virtual address. One of the plurality of processors is a file processor which accesses the main memory with a virtual address to transfer data between the main memory and an external memory. The cache memory receives the virtual address when the file processor writes to the main memory and if it contains a data block corresponding to the virtual address, it invalidates the corresponding data block. The address translation unit translates the address differently for the access from the file processor and the accesses from other processors.

    摘要翻译: 公开了一种具有地址转换单元的虚拟存储数据处理系统,该地址转换单元由位于连接到主存储器的存储器控​​制单元中的多个处理器共享。 多个处理器之一是作业处理器,其以虚拟地址访问主存储器以执行指令,并且包括用虚拟地址访问的高速缓冲存储器。 多个处理器之一是文件处理器,其以虚拟地址访问主存储器,以在主存储器和外部存储器之间传送数据。 当文件处理器写入主存储器时,缓存存储器接收虚拟地址,并且如果其包含与虚拟地址相对应的数据块,则使相应的数据块无效。 地址转换单元不同地翻译来自文件处理器的访问以及来自其他处理器的访问。

    Data processing system
    7.
    发明授权
    Data processing system 失效
    数据处理系统

    公开(公告)号:US4520441A

    公开(公告)日:1985-05-28

    申请号:US329949

    申请日:1981-12-11

    IPC分类号: G06F12/08 G06F12/10 G06F13/00

    CPC分类号: G06F12/1027 G06F12/0866

    摘要: A data processing system for supporting a virtual memory is disclosed. Prior to the start of main memory write operation, a processor checks to see if a store buffer has a vacant area to store data to be written into a main memory to execute a current instruction. If a page fault occurs during the main memory write operation, the processor continues to store the subsequent write data for the current instruction and the corresponding virtual or logical addresses in the store buffer to complete execution of the current instruction.

    摘要翻译: 公开了一种用于支持虚拟存储器的数据处理系统。 在主存储器写入操作开始之前,处理器检查存储缓冲器是否具有空闲区域以存储要写入主存储器中的数据以执行当前指令。 如果在主存储器写入操作期间发生页错误,则处理器继续存储当前指令的后续写入数据和存储缓冲器中的相应虚拟或逻辑地址,以完成当前指令的执行。

    Vector processor
    8.
    发明授权
    Vector processor 失效
    矢量处理器

    公开(公告)号:US4853890A

    公开(公告)日:1989-08-01

    申请号:US485396

    申请日:1983-04-15

    摘要: In a vector processor including pipeline processors and means for synchronously controlling each component, there is provided an FIFO memory for temporarily storing the output of each pipeline processor and for outputting the stored data, in the order of storing, to at least one of the pipeline processors. Since intermediate result of operation is temporarily stored in the FIFO memory, a simple microprogram can be used and thus the capacity of the memory for microprogram can be reduced even if the successive intermediate results for calculation of vector elements are overlapped within the loop of the microprogram.

    摘要翻译: 在包括流水线处理器的矢量处理器和用于同步控制每个组件的装置中,提供了一个FIFO存储器,用于临时存储每个流水线处理器的输出,并按存储顺序将存储的数据输出到至少一个流水线 处理器。 由于中间操作结果被临时存储在FIFO存储器中,所以可以使用简单的微程序,因此即使用于向量元素的计算的连续中间结果重叠在微程序循环内,微程序存储器的容量也可以减小 。

    Suspended instruction restart processing system based on a checkpoint
microprogram address
    9.
    发明授权
    Suspended instruction restart processing system based on a checkpoint microprogram address 失效
    基于检查点微程序地址的暂停指令重新启动处理系统

    公开(公告)号:US5003458A

    公开(公告)日:1991-03-26

    申请号:US111618

    申请日:1987-10-23

    IPC分类号: G06F11/14

    CPC分类号: G06F11/141

    摘要: Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

    摘要翻译: 在微程序控制数据处理装置中进行指令重新开始处理的方法和装置,其中,在指令暂停之后重启指令执行时,指令执行暂停时的数据处理装置的内部信息被保存在存储器中,之后 暂停原因清除过程执行保存的内部信息被恢复。 根据微程序的指定,存储与当前执行的微程序地址相关联的检查点地址。 暂停之后,执行删除处理,指令的执行使用检查点地址重新开始。 如果在暂停原因移除处理被执行之后没有存储检查点地址,则从主存储器的暂停指令的读取操作重新开始指令的执行。