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公开(公告)号：US20110284971A1
公开(公告)日：2011-11-24
申请号：US13109736
申请日：2011-05-17
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L21/823857 , H01L21/28088 , H01L27/092 , H01L29/513 , H01L29/518 , H01L29/66492
摘要： There are provided a semiconductor device in which the threshold voltage of a p-channel field effect transistor is reliably controlled to allow a desired characteristic to be obtained, and a manufacturing method thereof. As a heat treatment performed at a temperature of about 700 to 900° C. proceeds, in an element formation region, aluminum (Al) in an aluminum (Al) film is diffused into a hafnium oxynitride (HfON) film, and thereby added as an element to the hafnium oxynitride (HfON) film. In addition, aluminum (Al) and titanium (Ti) in a hard mask formed of a titanium aluminum nitride (TiAlN) film are diffused into the hafnium oxynitride (HfON) film, and thereby added as elements to the hafnium oxynitride (HfON) film.
摘要翻译： 提供一种可以可靠地控制p沟道场效应晶体管的阈值电压以获得期望特性的半导体器件及其制造方法。 当在700〜900℃左右的温度下进行热处理时，在元素形成区域中，将铝（Al）膜中的铝（Al）扩散到氮氧化铪（HfON）膜中， 铪氧氮化铪（HfON）膜的元素。 另外，由氮化钛（TiAlN）膜形成的硬掩模中的铝（Al）和钛（Ti）扩散到氮氧化铪（HfON）膜中，从而作为元素添加到氮氧化铪（HfON）膜 。
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公开(公告)号：US20120045876A1
公开(公告)日：2012-02-23
申请号：US13183996
申请日：2011-07-15
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842
摘要： There is provided a technology capable of preventing the increase in threshold voltages of n channel type MISFETs and p channel type MISFETs in a semiconductor device including CMISFETs having high dielectric constant gate insulation films and metal gate electrodes. When a rare earth element or aluminum is introduced into a Hf-containing insulation film which is a high dielectric constant gate insulation film for the purpose of adjusting the threshold value of the CMISFET, a threshold adjustment layer including a lanthanum film scarcely containing oxygen, and a threshold adjustment layer including an aluminum film scarcely containing oxygen are formed over the Hf-containing insulation film in an nMIS formation region and a pMIS formation region, respectively. This prevents oxygen from being diffused from the threshold adjustment layers into the Hf-containing insulation film and the main surface of a semiconductor substrate.
摘要翻译： 提供了能够防止包括具有高介电常数栅极绝缘膜和金属栅电极的CMISFET的半导体器件中的n沟道型MISFET和p沟道型MISFET的阈值电压增加的技术。 当为了调整CMISFET的阈值而将稀土元素或铝引入到作为高介电常数栅极绝缘膜的Hf的绝缘膜中时，包括几乎不含有氧的镧膜的阈值调整层和 在nMIS形成区域和pMIS形成区域中分别在Hf的绝缘膜上形成包含几乎不含氧的铝膜的阈值调整层。 这防止氧从阈值调节层扩散到含Hf的绝缘膜和半导体衬底的主表面。
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公开(公告)号：US08293632B2
公开(公告)日：2012-10-23
申请号：US12755058
申请日：2010-04-06
IPC分类号： H01L21/3205
CPC分类号： H01L21/823857
摘要： To improve productivity and performance of a CMISFET including a high-dielectric-constant gate insulating film and a metal gate electrode. An Hf-containing insulating film for a gate insulating film is formed over the main surface of a semiconductor substrate. A metal nitride film is formed on the insulating film. The metal nitride film in an nMIS formation region where an n-channel MISFET is to be formed is selectively removed by wet etching using a photoresist pattern on the metal nitride films a mask. Then, a threshold adjustment film containing a rare-earth element is formed. The Hf-containing insulating film in the nMIS formation region reacts with the threshold adjustment film by heat treatment. The Hf-containing insulating film in a pMIS formation region where a p-channel MISFET is to be formed does not react with the threshold adjustment film because of the existence of the metal nitride film. Then, after removing the unreacted threshold adjustment film and the metal nitride film, metal gate electrodes are formed in the nMIS formation region and the pMIS formation region.
摘要翻译： 提高包括高介电常数栅极绝缘膜和金属栅电极在内的CMISFET的生产率和性能。 在半导体衬底的主表面上形成用于栅极绝缘膜的含Hf绝缘膜。 在绝缘膜上形成金属氮化物膜。 通过在金属氮化物膜上使用光刻胶图案的掩模，通过湿式蚀刻选择性地去除要形成n沟道MISFET的nMIS形成区域中的金属氮化物膜。 然后，形成含有稀土元素的阈值调节膜。 nMIS形成区域中的含Hf绝缘膜通过热处理与阈值调节膜反应。 由于存在金属氮化物膜，所以要形成p沟道MISFET的pMIS形成区域中的含Hf绝缘膜不会与阈值调节膜反应。 然后，在除去未反应的阈值调整膜和金属氮化物膜之后，在nMIS形成区域和pMIS形成区域中形成金属栅电极。
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公开(公告)号：US20100320542A1
公开(公告)日：2010-12-23
申请号：US12782457
申请日：2010-05-18
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823857 , H01L27/092
摘要： To improve the performance of a CMISFET having a high-k gate insulating film and a metal gate electrode. An n-channel MISFET has, over the surface of a p-type well of a semiconductor substrate, a gate electrode formed via a first Hf-containing insulating film serving as a gate insulating film, while a p-channel MISFET has, over the surface of an n-type well, another gate electrode formed via a second Hf-containing insulating film serving as a gate insulating film. These gate electrodes have a stack structure of a metal film and a silicon film thereover. The first Hf-containing insulating film is an insulating material film comprised of Hf, a rare earth element, Si, O, and N or comprised of Hf, a rare earth element, Si, and O, while the second Hf-containing insulating film is an insulating material film comprised of Hf, Al, O, and N or comprised of Hf, Al, and O.
摘要翻译： 为了提高具有高k栅极绝缘膜和金属栅电极的CMISFET的性能。 n沟道MISFET在半导体衬底的p型阱的表面上具有通过用作栅极绝缘膜的第一Hf绝缘膜形成的栅电极，而p沟道MISFET具有 n型阱的表面，通过用作栅极绝缘膜的第二Hf含量绝缘膜形成的另一个栅电极。 这些栅电极具有金属膜和其上的硅膜的堆叠结构。 第一含Hf绝缘膜是包括Hf，稀土元素，Si，O和N或由Hf，稀土元素，Si和O构成的绝缘材料膜，而第二Hf含量绝缘膜 是由Hf，Al，O和N组成或由Hf，Al和O构成的绝缘材料膜。
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公开(公告)号：US08536017B2
公开(公告)日：2013-09-17
申请号：US13363312
申请日：2012-01-31
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 μm or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 μm or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300° C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO2) and remove a void in the upper portion of the narrower trench.
摘要翻译： 在半导体衬底的主表面上形成聚硅氮烷膜，使得埋在宽度为0.2μm或更小的沟槽中的聚硅氮烷膜的上表面水平高于衬垫绝缘膜的上表面水平， 埋入宽度为1.0μm以上的沟槽中的聚硅氮烷膜的水平比焊垫绝缘膜低。 然后，在300℃以上进行热处理，将聚硅氮烷膜转换为由氧化硅（SiO 2）构成的第一掩埋膜，并且在较窄的沟槽的上部除去空隙。
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公开(公告)号：US20070054503A1
公开(公告)日：2007-03-08
申请号：US11510679
申请日：2006-08-28
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/0228 , C23C16/44 , C23C16/45525 , H01L21/02164 , H01L21/02181 , H01L21/02189 , H01L21/022 , H01L21/28079 , H01L21/28194 , H01L21/3141 , H01L29/495 , H01L29/517
摘要： A method of forming a film on a substrate includes a first step of carrying out first film formation on an insulation layer formed on the substrate by an ALD process, and a second step of carrying out second film formation in continuation to the first step by a CVD process.
摘要翻译： 在衬底上形成膜的方法包括：通过ALD工艺在形成在衬底上的绝缘层上进行第一膜形成的第一步骤;以及第二步骤，通过第一步骤进行第二膜形成 CVD工艺。
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公开(公告)号：US07618855B2
公开(公告)日：2009-11-17
申请号：US11540506
申请日：2006-10-02
IPC分类号： H01L21/8238
CPC分类号： H01L21/823835 , H01L21/28052 , H01L21/28097 , H01L21/28518 , H01L29/4975 , H01L29/6659
摘要： A technology capable of improving the yield in a manufacturing process of a MISFET with a gate electrode formed of a metal silicide film. A gate insulating film is formed on a semiconductor substrate and silicon gate electrodes formed of a polysilicon film are formed on the gate insulating film. Then, after a silicon oxide film is formed so as to cover the silicon gate electrodes, a surface of the silicon oxide film is polished by CMP, thereby exposing the surface of the silicon gate electrodes. Subsequently, a patterned insulating film is formed on the silicon oxide film. Thereafter, an adhesion film is formed on the silicon oxide film and the insulating film. Then, a nickel film is formed on the adhesion film. Thereafter, a silicide reaction is caused to occur between the silicon gate electrode and the nickel film via the adhesion film.
摘要翻译： 一种能够通过由金属硅化物膜形成的栅电极在MISFET的制造工艺中提高产量的技术。 在半导体衬底上形成栅极绝缘膜，在栅极绝缘膜上形成由多晶硅膜形成的硅栅电极。 然后，在形成氧化硅膜以覆盖硅栅电极之后，通过CMP抛光氧化硅膜的表面，从而暴露硅栅电极的表面。 随后，在氧化硅膜上形成图案化的绝缘膜。 此后，在氧化硅膜和绝缘膜上形成粘合膜。 然后，在粘合膜上形成镍膜。 此后，通过粘合膜在硅栅电极和镍膜之间发生硅化物反应。
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8.发明申请公开(公告)号：US20070221970A1
公开(公告)日：2007-09-27
申请号：US11715353
申请日：2007-03-08
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823842 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： In a manufacturing process of a semiconductor device having a CMISFET, first, a silicon film and a first metal film made of a first metal are reacted with each other through heat treatment, thereby forming a gate electrode of a p-channel type MISFET and a dummy gate electrode of an n-channel type MISFET, which are formed of metal silicide. Subsequently, an insulating film is formed so as to cover the gate electrode but expose the dummy electrode, and then, a metal film formed of a second metal having a work function lower than that of the first metal. The metal film contacts with the dummy gate but not with the gate electrode due to the insulating film interposing therebetween. Thereafter, through heat treatment, the dummy gate electrode and the metal film are reacted with each other to form a gate electrode of the n-channel type MISFET.
摘要翻译： 在具有CMISFET的半导体器件的制造工艺中，首先，由第一金属制成的硅膜和第一金属膜通过热处理彼此反应，从而形成p沟道型MISFET的栅电极和 由金属硅化物形成的n沟道型MISFET的虚拟栅电极。 随后，形成绝缘膜以覆盖栅电极，但暴露虚拟电极，然后形成由功函数低于第一金属功函数的第二金属形成的金属膜。 金属膜与虚拟栅极接触，但由于绝缘膜介于其间，与栅电极接触。 此后，通过热处理，虚拟栅电极和金属膜彼此反应，形成n沟道型MISFET的栅电极。
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公开(公告)号：US20050167762A1
公开(公告)日：2005-08-04
申请号：US11037333
申请日：2005-01-19
申请人： Masaru Kadoshima , Koji Akiyama , Morifumi Ohno
发明人： Masaru Kadoshima , Koji Akiyama , Morifumi Ohno
IPC分类号： H01L21/28 , H01L21/336 , H01L21/768 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/76 , H01L29/78 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28176 , H01L21/28202 , H01L21/823835 , H01L21/823842 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A technique capable of reducing threshold voltage and reducing high-temperature heat treatment after forming a gate electrode is provided. An n-type MIS transistor or a p-type MIS transistor is formed on an active region isolated by an element isolation region of a semiconductor substrate. In the n-type MIS transistor, a gate electrode is formed through a gate insulating film, and the gate electrode is composed of a hafnium silicide film. On the other hand, in the p-type MIS transistor, a gate electrode is formed through a gate insulating film, and the gate electrode is composed of a platinum silicide film. Also, the gate electrodes are formed after the activation annealing (heat treatment) for activating impurities implanted into a source region and a drain region.
摘要翻译： 提供了一种能够在形成栅电极之后降低阈值电压并降低高温热处理的技术。 在由半导体衬底的元件隔离区隔离的有源区上形成n型MIS晶体管或p型MIS晶体管。 在n型MIS晶体管中，通过栅极绝缘膜形成栅电极，栅电极由硅化铪膜构成。 另一方面，在p型MIS晶体管中，通过栅极绝缘膜形成栅电极，栅电极由铂硅化物膜构成。 此外，在用于激活注入到源极区域和漏极区域中的杂质的活化退火（热处理）之后，形成栅电极。
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公开(公告)号：US07511338B2
公开(公告)日：2009-03-31
申请号：US11515797
申请日：2006-09-06
IPC分类号： H01L23/62
CPC分类号： H01L21/823842 , H01L21/28185 , H01L29/6659 , H01L29/7833
摘要： An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and the p channel MIS transistor are simultaneously formed by patterning ruthenium film deposited on a gate insulator. Next, by introducing oxygen into each of the gate electrodes, the gate electrodes are transformed into those having high work function. Thereafter, by selectively reducing the gate electrode of the n channel MIS transistor, it is transformed into a gate electrode having low work function.
摘要翻译： 本发明的一个目的是简化n沟道MIS晶体管和具有由金属材料形成的栅电极的p沟道MIS晶体管的制造工艺。 为了实现，通过图案化沉积在栅极绝缘体上的钌膜，同时形成n沟道MIS晶体管和p沟道MIS晶体管中的每一个的栅电极。 接下来，通过将氧气引入每个栅电极，将栅电极转变为具有高功函数的栅电极。 此后，通过选择性地还原n沟道MIS晶体管的栅电极，将其转换成具有低功函数的栅电极。
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