公开(公告)号：US06909644B2

公开(公告)日：2005-06-21

申请号：US09791815

申请日：2001-02-26

申请人： Shinya Fujioka ,  Hitoshi Ikeda ,  Masato Matsumiya

发明人： Shinya Fujioka ,  Hitoshi Ikeda ,  Masato Matsumiya

IPC分类号： G11C11/409 ,  G11C11/00 ,  G11C11/401 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/00

CPC分类号： G11C7/065 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2211/4013

摘要： The present invention provides a semiconductor memory device of a twin-storage type having an operation control method and a circuit structure that achieve a higher process rate, a less power consumption, and a smaller chip area. This semiconductor memory device includes bit lines in pairs, a sense amplifier connected to each pair of the bit lines, a first memory cell connected to one bit line of each pair of the bit lines, a second memory cell that is connected to the other bit line of each pair of the bit lines and stores the inverted data of the data stored in the first memory cell. This semiconductor memory device is characterized by not having means to pre-charge the bit lines to a predetermined potential. The semiconductor memory device of the present invention is also characterized by including a control circuit that controls the sense amplifier to start a pull-down operation after starting a pull-up operation.

摘要翻译： 本发明提供一种双存储型半导体存储器件，其具有实现更高处理速率，更少功耗和更小芯片面积的操作控制方法和电路结构。 该半导体存储器件包括成对的位线，连接到每对位线的读出放大器，连接到每对位线的一个位线的第一存储器单元，连接到另一个位的第二存储器单元 并且存储存储在第一存储单元中的数据的反相数据。 该半导体存储器件的特征在于没有将位线预充电到预定电位的装置。 本发明的半导体存储器件的特征还在于包括控制电路，其控制读出放大器在开始上拉操作之后开始下拉操作。

公开(公告)号：US06344990B1

公开(公告)日：2002-02-05

申请号：US09652015

申请日：2000-08-31

申请人： Masato Matsumiya ,  Shinya Fujioka ,  Kimiaki Satoh ,  Toru Miyabo

发明人： Masato Matsumiya ,  Shinya Fujioka ,  Kimiaki Satoh ,  Toru Miyabo

IPC分类号： G11C506

CPC分类号： G11C7/02 ,  G11C7/1042 ,  G11C7/18 ,  G11C11/406 ,  G11C11/4097 ,  G11C2211/4013

摘要： A memory circuit including a memory cell array. The memory cell array has a first word line group connected to a pair of memory cells associated with a first bit line pair including first and third bit lines, and a second word line group, connected to a pair of memory cells associated with a second bit line pair including second and fourth bit lines. First and second sense amplifier groups are positioned one on each side of the memory array, and are connected to the first and second bit line pair, respectively. When any word line of the first word line group is driven, the first sense amplifier group is activated to drive the first word line group in reverse phase, and the second sense amplifier group is kept in the inactive state to keep the second word line group at the precharge level.

摘要翻译： 一种包括存储单元阵列的存储电路。 存储单元阵列具有连接到与包括第一和第三位线的第一位线对相关联的一对存储器单元的第一字线组，以及连接到与第二位相关联的一对存储器单元的第二字线组 包括第二和第四位线的线对。 第一和第二读出放大器组分别位于存储器阵列的每一侧上，并且分别连接到第一和第二位线对。 当驱动第一字线组的任何字线时，第一读出放大器组被激活以反相驱动第一字线组，并且第二读出放大器组保持在非活动状态以保持第二字线组 在预充电水平。

公开(公告)号：US20100220540A1

公开(公告)日：2010-09-02

申请号：US12718808

申请日：2010-03-05

申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

公开(公告)号：US07706209B2

公开(公告)日：2010-04-27

申请号：US11313963

申请日：2005-12-22

申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

IPC分类号： G11C8/08

CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

摘要： A semiconductor device, including a word line driver for driving a word line connected to a memory cell in a memory cell array and for resetting the word line when the memory cell changes from an activated to a standby state. The reset level of the word line driver is set when resetting of the word line is performed, and may be switched between first and second potentials. A word line reset level generating circuit varies the amount of negative potential current supply in accordance with memory cell array operating conditions. The semiconductor device includes a plurality of power source circuits, each having an oscillation circuit and a capacitor, for driving the capacitor via an oscillation signal outputted by the oscillation circuit. At least some power source circuits share a common oscillation circuit, and different capacitors are driven via the common oscillation signal.

摘要翻译： 一种半导体器件，包括用于驱动连接到存储单元阵列中的存储单元的字线的字线驱动器，以及当存储器单元从激活状态变为待机状态时重新设定字线。 当执行字线的复位时，字线驱动器的复位电平被设置，并且可以在第一和第二电位之间切换。 字线复位电平发生电路根据存储单元阵列工作条件改变负电位电流供给量。 半导体器件包括多个电源电路，每个电源电路具有振荡电路和电容器，用于经由振荡电路输出的振荡信号来驱动电容器。 至少一些电源电路共用一个共同的振荡电路，而不同的电容通过公共振荡信号驱动。

公开(公告)号：US20060294322A1

公开(公告)日：2006-12-28

申请号：US11512319

申请日：2006-08-30

申请人： Yasurou Matsuzaki ,  Takaaki Suzuki ,  Masafumi Yamazaki ,  Kenichi Kawasaki ,  Shinnosuke Kamata ,  Ayako Sato ,  Masato Matsumiya

发明人： Yasurou Matsuzaki ,  Takaaki Suzuki ,  Masafumi Yamazaki ,  Kenichi Kawasaki ,  Shinnosuke Kamata ,  Ayako Sato ,  Masato Matsumiya

IPC分类号： G06F13/28

CPC分类号： G11C8/16 ,  G06F13/1605 ,  G11C7/1039 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/18 ,  G11C11/24 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/409 ,  G11C11/4093 ,  G11C2207/107 ,  G11C2207/108

摘要： A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

公开(公告)号：US06430102B2

公开(公告)日：2002-08-06

申请号：US09859259

申请日：2001-05-18

申请人： Kaoru Mori ,  Masato Matsumiya

发明人： Kaoru Mori ,  Masato Matsumiya

IPC分类号： G11C700

CPC分类号： G11C17/18 ,  G11C5/147

摘要： To supply a ground potential Vss to a starter signal level shifter and a fuse information latch circuit on the basis of a fuse starter signal of which low level is shifted from the ground potential Vss to a negative voltage Vnn by the starter signal level shifter until the fuse information is latched to the fuse information latch circuit. After the foregoing fuse information is latched, a finally attained potential is supplied to the starter signal level shifter and the fuse information latch circuit. Therefore, it is possible to latch without shifting the low level, so that it becomes possible to easily shift the low level from the ground potential Vss to the negative voltage Vnn after latching.

摘要翻译： 基于由起动器信号电平移位器将低电平从接地电位Vss移位到负电压Vnn的熔丝启动器信号，向起动信号电平移位器和熔丝信息锁存电路提供接地电位Vss，直到 熔丝信息被锁存到熔丝信息锁存电路。 在上述熔丝信息被锁存之后，将最终达到的电位提供给起动信号电平移位器和熔丝信息锁存电路。 因此，可以在不移动低电平的情况下锁存，使得可以在锁存之后容易地将低电平从接地电位Vss移位到负电压Vnn。

公开(公告)号：US06317353B1

公开(公告)日：2001-11-13

申请号：US09536449

申请日：2000-03-28

申请人： Toshimi Ikeda ,  Masato Matsumiya ,  Masato Takita

发明人： Toshimi Ikeda ,  Masato Matsumiya ,  Masato Takita

IPC分类号： G11C506

CPC分类号： G11C5/063 ,  G11C5/14

摘要： A power supply line is formed over a memory cell array which has arranged a plurality of memory cells using a metal wiring layer M1 which is disposed on the side closest to the memory cell array, of all the metal wiring layers. The power supply lines are formed over the memory cell array using not only an upper metal wiring layer M2 but the metal wiring layer M1 so that the wiring resistance of the power supply lines may decrease and a sufficient amount of current can be supplied to the power supply lines. Consequently, the circuits supplied with an electric current through the power supply lines become capable of high-speed operation. This is particularly effective for the high-speed operation of the circuits arranged around the memory cell array. The power supply line formed using the lower metal wiring layer M1 is connected over the memory cell array to a power supply line which is formed using the metal wiring layer M2 on the upper layer than the metal wiring layer M1. Therefore, the netlike configuration of the power supply lines can be made with higher density compared to conventional ones.

摘要翻译： 电源线形成在存储单元阵列上，该存储单元阵列使用布置在最靠近存储单元阵列的一侧的金属布线层M1布置了多个存储单元。 电源线不仅使用上金属布线层M2而且金属布线层M1形成在存储单元阵列的上方，使得电源线的布线电阻可能降低，并且能够向电源提供足够的电流量 供应线。 因此，通过电源线提供电流的电路变得能够高速运行。 这对于布置在存储单元阵列周围的电路的高速操作特别有效。 使用下金属布线层M1形成的电源线通过存储单元阵列连接到使用上层的金属布线层M2形成的电源线，而不是金属布线层M1。 因此，与常规电源线相比，可以以更高的密度制造电源线的网状结构。

公开(公告)号：US06262930B1

公开(公告)日：2001-07-17

申请号：US09612281

申请日：2000-07-07

申请人： Kaoru Mori ,  Masato Matsumiya ,  Ayako Kitamoto ,  Shinichi Yamada ,  Yuki Ishii ,  Hideki Kanou ,  Masato Takita

发明人： Kaoru Mori ,  Masato Matsumiya ,  Ayako Kitamoto ,  Shinichi Yamada ,  Yuki Ishii ,  Hideki Kanou ,  Masato Takita

IPC分类号： G11C700

CPC分类号： G11C7/06

摘要： To reduce current consumption, there is provided a circuit for each bank, comprising selection circuits 26 through 28 each for selecting either a normal supply voltage Vii or a higher supply voltage Vjj as a supply voltage VH0 in response to a selection control signals SC0 and *SC0, a selection control circuit 22 for generating the signals SC0 and *SC0 to make the selection circuits select Vii when a bank activation signal BRAS0 is inactive and Vjj for a predetermined period in response to activation of BRAS0, and sense amplifier driving circuits 111 through 113 for supplying the ground voltage and VH0 to the sense amplifier rows in response to activation of sense amplifier control signals. To stabilize the output voltage Vii of the power supply circuit having a NMOS transistor, the drain electrode, gate and source electrodes of which are at VCC, VG and approximately Vii=VG−Vth, where Vth is the threshold voltage of the NMOS transistor 45, a leak circuit is employed. The leak circuit has a NMOS transistor connected between Vii and ground. Wasteful power consumption by the current flowing to the leak circuit is negligibly small, e.g. 1 to 10 &mgr;A, and the variation of the supply voltage Vii reduces effectively.

摘要翻译： 为了减少电流消耗，为每个存储体提供一个电路，其中包括选择电路26至28，每个选择电路26至28用于响应于选择控制信号SC0和*选择正常电源电压Vii或较高电源电压Vjj作为电源电压VH0， SC0，用于产生信号SC0和* SC0的选择控制电路22，以使得当存储体激活信号BRAS0不活动时选择电路选择Vii，并响应于BRAS0的激活而在预定时间段内选择Vjj，读出放大器驱动电路111通过 113，用于响应于感测放大器控制信号的激活而将接地电压和VH0提供给读出放大器行。 为了稳定具有NMOS晶体管的电源电路的输出电压Vii，其漏电极，栅极和源电极处于VCC，VG和大约Vii = VG-Vth，其中Vth是NMOS晶体管45的阈值电压 ，采用泄漏电路。 泄漏电路具有连接在Vii和地之间的NMOS晶体管。 通过流向泄漏电路的电流浪费的功率消耗可忽略不计，例如， 1〜10μA，电源电压Vii的变化有效降低。

公开(公告)号：US06169701A

公开(公告)日：2001-01-02

申请号：US08946586

申请日：1997-10-07

申请人： Satoshi Eto ,  Masato Matsumiya ,  Hideki Kanou

发明人： Satoshi Eto ,  Masato Matsumiya ,  Hideki Kanou

IPC分类号： G11C800

CPC分类号： G11C7/065

摘要： In the present invention, the gate electrodes of the bit line transfer gates for bit line pair selection that perform connection and isolation of the sense amplifiers and bit line pairs are put into floating condition during activation of the sense amplifier in the active period. Thus, a system is adopted according to which the potential of the bit line is driven to power source voltage Vcc or high voltage corresponding thereto by the sense amplifier in the active condition, the pre-charging potential of the bit line pair being made lower than half the power source voltage Vcc, for example ground potential Vss. Thanks to the amplification action of the sense amplifier, by utilising the fact that one side of the plurality of bit line pairs is inevitably driven from low potential to the power source voltage Vcc level or high voltage corresponding thereto, the potential of the gate electrodes which are in floating condition is boosted higher due to capacitative coupling, enabling the potential of the bit line on rewriting to be boosted to a voltage driven by the sense amplifier, for example power source voltage.

摘要翻译： 在本发明中，在激活期间的感测放大器的激活期间，执行读出放大器和位线对的连接和隔离的位线对选择的位线传输门的栅极被置于浮置状态。 因此，采用一种系统，根据该系统，位线的电位在激活状态下由读出放大器驱动到电源电压Vcc或与其对应的高电压，位线对的预充电电位低于 电源电压Vcc的一半，例如地电位Vss。 由于读出放大器的放大动作，通过利用多个位线对的一侧不可避免地从低电位驱动到对应于其的电源电压Vcc电平或高电压的事实，栅电极的电位 处于浮置状态的电容由于电容耦合而被提升得更高，使得重写中的位线的电位可以升高到由读出放大器驱动的电压，例如电源电压。

公开(公告)号：US6115316A

公开(公告)日：2000-09-05

申请号：US342060

申请日：1999-06-29

申请人： Kaoru Mori ,  Masato Matsumiya ,  Ayako Kitamoto ,  Shinichi Yamada ,  Yuki Ishii ,  Hideki Kanou ,  Masato Takita

发明人： Kaoru Mori ,  Masato Matsumiya ,  Ayako Kitamoto ,  Shinichi Yamada ,  Yuki Ishii ,  Hideki Kanou ,  Masato Takita

IPC分类号： G11C7/06 ,  G11C8/00

CPC分类号： G11C7/06

摘要： To reduce current consumption, there is provided a circuit for each bank, comprising selection circuits 26 through 28 each for selecting either a normal supply voltage Vii or a higher supply voltage Vjj as a supply voltage VH0 in response to a selection control signals SC0 and *SC0, a selection control circuit 22 for generating the signals SC0 and *SC0 to make the selection circuits select Vii when a bank activation signal BRAS0 is inactive and Vjj for a predetermined period in response to activation of BRAS0, and sense amplifier driving circuits 111 through 113 for supplying the ground voltage and VH0 to the sense amplifier rows in response to activation of sense amplifier control signals. To stabilize the output voltage Vii of the power supply circuit having a NMOS transistor, the drain electrode, gate and source electrodes of which are at VCC, VG and approximately Vii=VG-Vth, where Vth is the threshold voltage of the NMOS transistor 45, a leak circuit is employed. The leak circuit has a NMOS transistor connected between Vii and ground. Wasteful power consumption by the current flowing to the leak circuit is negligibly small, e.g. 1 to 10 .mu.A, and the variation of the supply voltage Vii reduces effectively.

摘要翻译： 为了减少电流消耗，为每个存储体提供一个电路，其中包括选择电路26至28，每个选择电路26至28用于响应于选择控制信号SC0和*选择正常电源电压Vii或较高电源电压Vjj作为电源电压VH0， SC0，用于产生信号SC0和* SC0的选择控制电路22，以使得当存储体激活信号BRAS0不活动时选择电路选择Vii，并响应于BRAS0的激活而在预定时间段内选择Vjj，读出放大器驱动电路111通过 113，用于响应于感测放大器控制信号的激活而将接地电压和VH0提供给读出放大器行。 为了稳定具有NMOS晶体管的电源电路的输出电压Vii，其漏电极，栅极和源电极处于VCC，VG和大约Vii = VG-Vth，其中Vth是NMOS晶体管45的阈值电压 ，采用泄漏电路。 泄漏电路具有连接在Vii和地之间的NMOS晶体管。 通过流向泄漏电路的电流浪费的功率消耗可忽略不计，例如， 1至10μA，并且电源电压Vii的变化有效降低。